Physical Design Engineer at Texas Instruments Santa Clara, CA

Dan Cummins Ford Lincoln; Santa Clara (CA); On-site; USD 125,000 - 234,000; Full time

Job summary

Texas Instruments in Santa Clara, CA is seeking a Physical Design Engineer to drive high‑speed SerDes integration for automotive and multimedia applications.

You will own physical implementation from synthesis to CTS, DRC/LVS checks, and tapeout readiness, collaborating with analog and digital teams to deliver timing-accurate, power-efficient sub-systems for next‑generation chips.

Qualifications

• 12 years of relevant experience.
• Expertise with Cadence toolset for PnR, timing analysis, and synthesis.
• Familiarity with multi-clock domain CTS and debugging.
• Strong ability to understand physical realizations of logic structures and clocking.
• Experience through all aspects of digital sub-chip delivery including power, IR, EM, DRC, LVS, etc.
• Skilled in writing TCL scripts for editing the netlist for cloning, load balancing, and ECOs.

Responsibilities

• Synthesis, floorplan, placement, clock-tree synthesis and debugging, routing, timing closure, power analysis, IR-drop, EM-checks.
• Physical verification such as DRC, LVS, antenna checks.
• Tapeout in Digital-on-top flows or delivery of timing-clean sub-chip for top-level integration in Analog-on-Top flows.
• Ensure device meets spec requirements for power, performance, and area.
• Develop solutions to complex problems through assessment of various techniques and approaches.
• Plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and detailed instructions on new assignments.
• Communicate routinely with analog and digital design engineers, present information, and participate actively in work groups.

Skills

Large-scale design

CTS familiarity

Physical realization understanding

Team collaboration

Tools

Cadence toolset

TCL scripting

Job description

Physical Design Engineer

Santa Clara, CA.

Change the world. Love your job.

We enable the next generation of Audio‑Video in cars, whether it is to enable self‑driving in an ADAS system or rear‑seat entertainment in an IVI system. You will be part of the team enabling a high‑end experience in the future generation of cars.

In this position, you will be responsible for the physical design of high‑speed mixed‑signal SerDes circuits using state‑of‑the‑art process technology. The work involves multi‑million gate designs with complex clock‑trees and high‑speed interfaces to analog components.

Responsibilities

• Synthesis, floorplan, placement, clock‑tree synthesis and debugging, routing, timing closure, power analysis, IR‑drop, EM‑checks.
• Physical verification such as DRC, LVS, antenna checks.
• Tapeout in Digital‑on‑top flows or delivery of timing‑clean sub‑chip for top‑level integration in Analog‑on‑Top flows.
• Ensure device meets spec requirements for power, performance, and area.
• Develop solutions to complex problems through assessment of various techniques and approaches.
• Plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and detailed instructions on new assignments.
• Communicate routinely with analog and digital design engineers, present information, and participate actively in work groups.

Minimum Requirements

• 12 years of relevant experience.
• Expertise with Cadence toolset for PnR, timing analysis, and synthesis.
• Familiarity with multi‑clock domain clock‑tree synthesis (CTS) and debugging.
• Strong ability to understand physical realizations of logic structures and clocking.
• Experience through all aspects of digital sub‑chip delivery including power, IR, EM, DRC, LVS, etc.
• Skilled in writing TCL scripts for editing the netlist for cloning, load balancing, and ECOs.
• Ability to work with multi‑million gate designs.
• Ability to solve problems using a systematic approach.

Preferred Qualifications

• Demonstrated strong analytical and problem‑solving skills.
• Strong verbal and written communication skills.
• Ability to work in teams and collaborate effectively with people in different functions.
• Strong time management skills that enable on‑time project delivery.
• Demonstrated ability to build strong, influential relationships.
• Ability to work effectively in a fast‑paced and rapidly changing environment.
• Ability to take initiative and drive for results.

Compensation

Base pay range: $125,000 – $234,000 per year. Base pay is one part of our total compensation package and is determined within a range, depending on skills, qualifications, experience, and location.

Eligibility

ECL/GTC Required: Yes.

About Texas Instruments

Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems.

We empower our employees to truly own their career and development, and we encourage diversity and inclusion. We are an equal‑opportunity employer and support a diverse, inclusive work environment. All qualified applicants will receive consideration without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status or any other characteristic protected by federal, state, or local laws.