Photonics AI Engineer — Tapeout & AI Automation

Georgian

Santa Clara (CA)

On-site

USD 160,000 - 210,000

Full time

10 days ago

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Job summary

Xanadu is hiring a Photonics AI Engineer to own layout and physical verification on a fast-paced path-finding team. You will transform validated components into tapeout-ready devices with test structures and full mask sets, driving automation to accelerate production.

Proficiency in Python, gdsfactory, IPKISS, KLayout, GDSII/OASIS, and agentic AI tooling is essential. Join a mission to build useful quantum computers and work alongside fabrication and test engineers to meet tight deadlines.

Qualifications

Fluency with modern AI tooling in day-to-day work (coding agents, LLM-driven automation, or agentic pipelines).
Participated in multiple tapeouts with ownership of layout, verification, and sign-off.
Enthusiasm for adopting new AI capabilities quickly and reshaping workflow around them.
Interest in applying ML/AI to design automation problems; prior hands-on experience in any domain is a plus.
BSc in Engineering, Physics, or a related field.
Strong experience with scripted photonic mask design and layout using gdsfactory, IPKISS, KLayout, or similar.
Experience generating production layout in GDSII/OASIS for dedicated full mask sets.
Solid experience with physical verification, including DRC and LVS with foundry-provided and custom rule decks.
Experience working from a PDK or a library of reusable layout building blocks.
Strong Python skills, including testing, code review, and version control.
Attention to detail combined with the judgement to know which checks matter under schedule pressure.
Comfortable operating in a fast-paced environment with hard external deadlines.

Responsibilities

Own GDS/OASIS mask layout end to end for test structures, path-finding vehicles, and production tapeouts.
Translate circuit schematics and component libraries into hierarchical, verified device layouts using scripted layout frameworks.
Own the path from PDK to tapeout, keeping the flow from released building blocks to a signed-off mask set fast and repeatable.
Build automated routing, floorplanning, and assembly tooling for large-scale photonic circuits, targeting minimum routing loss and footprint.
Own physical verification: DRC, LVS, connectivity and netlist integrity, custom rule decks, and mask data preparation.
Build agentic AI tooling for layout and verification: generating and refactoring layout code, triaging DRC violations, generating test-structure and DOE arrays, reconciling schematics against layout, and assembling tapeout review packages.
Own the tapeout process itself, including reticle floorplan, checklists, sign-off criteria, and submission to foundry partners.
Design test structures and on-chip monitors so the returning wafer answers the questions the design team actually asked.
Work closely with component designers, fabrication engineers, and test engineers to keep layout practice aligned with process capability.