Package Technology, Signal & Power Integrity Lead

AIDAChip Inc; San Francisco (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

AIDAChip Inc. in the SF Bay Area is seeking a Package Technology, Signal & Power Integrity Lead to own the cross‑disciplinary packaging and interface stack, and to decide what 'correct' means for each AI teammate before tapeout.

You will shape the die‑to‑package‑to‑board handoffs, set measurable criteria, and drive customer-ready methodology with forward‑deployed engineers. This role rewards hands‑on depth, system‑level thinking, and clear specification of behaviors for complex chip packages in

Qualifications

• 10+ years in packaging, signal and power integrity with deep hands-on depth in at least two areas.
• Experience bringing die/package/board together with advanced packaging (2.5D/3D) or high‑speed interfaces.
• Ability to define 'correct' behavior and articulate system-level requirements.

Responsibilities

• Own packaging and SI/PI methodology depth and set 'correct' criteria for customer-ready results.
• Create customer playbooks translating packaging and interface standards into repeatable deployments.
• Lead die/package/board seam work, addressing cross-boundary issues before tapeout.

Skills

Packaging

Signal integrity

Power integrity

PDN / IR-drop

High-speed interfaces

Chip-package co-design

DDR / PCIe / UCIe

Job description

Package Technology, Signal & Power Integrity Lead

SF Bay Area, CA

AIDAChip is the Alignment OS for AI-native silicon engineering teams — the first AI platform built for chip design teams, not just individuals. Chip design today is fragmented across disciplines, tools, and handoffs, so intent gets lost and work drifts. We're the shared nervous system that keeps intent, knowledge, and execution aligned from specification to tapeout.

The Role

You are the human authority on package technology, signal, and power integrity for that system. You decide what "correct" means for each package and integrity AI teammate, when it's good enough to put in front of a customer, and how they behave as a set rather than as point tools. Everything you shape ships to someone with a tapeout date and a product that has to work in the real world, and the AI does not do the engineering for you. You are the reason it gets good.

Key responsibilities

• Every package & integrity AI teammate on the platform — package design, power integrity (PDN, IR-drop), signal integrity & high-speed interfaces, and package-level integration (plus the technology / PDK and flow pieces they lean on), and the handoffs between them. You set what "correct" means for each, the bar for putting it in front of a customer, and how they behave as a system rather than point tools.
• Customer playbooks — turn a customer's packaging and signal / power-integrity methodology, interface standards, and integration signoff criteria into something repeatable we can deploy. This is customer-facing work. _You'll partner with our forward-deployed engineers, who own the deployment relationship — you own the package / SI-PI methodology depth._
• chip package board seam — where the die meets the package meets the board: signal and power integrity, thermal, and chiplet / 2.5D-3D interfaces. This is exactly where cross-boundary bugs live, and most teams under‑own it. We can't.

You may be a good fit if you have

• 10+ years in packaging / signal & power integrity, with deep hands-on depth in at least two of package design, power integrity (PDN / IR-drop), and signal integrity / high-speed interfaces — and credible in the third. The breadth is the job, not a bonus.
• Multiple products taken to production where die, package, and board had to close together — some with advanced packaging (2.5D / 3D, chiplets, interposers) or high‑speed interfaces.
• Package & power integrity: I/O planning, PDN design, IR-drop analysis, package substrate, and thermal.
• Signal integrity: high-speed interface design and analysis, crosstalk, channel / link budgets; fluency with interface standards (DDR, PCIe, UCIe, SerDes).
• Chip‑package co‑design and integration, coordinating across foundry / PDK enablement and EDA flows.
• A considered opinion on where the chip package board crossings actually break — and how to catch it earlier.
• Writing clear enough to specify behavior for a system that follows your words literally. This matters more here than in a normal packaging or SI/PI role.

Strong candidates may also have experience with

• Advanced packaging — chiplets, 2.5D / 3D, interposers, heterogeneous integration.
• Optical interconnects and related packaging technologies — co-packaged optics, silicon photonics, optical I/O.
• Foundry / PDK enablement or EDA‑flow / CAD methodology ownership.
• Hands‑on time with LLMs or agentic tooling — even if it went badly. We'd rather hear what failed.
• Automation / scripting (Python) for SI / PI or package‑level analysis.

How we're different

• Evidence over vibes: nothing is "done" until it's proven — results carry their proof, claims are verified before they're asserted, and failures surface loudly instead of slipping through
• Measured, not narrated: if it isn't measured, it did not happen — we decide on data in a shared system of record, not on how good the update sounded
• Agent leverage: every person directs a fleet of AI teammates and delivers at a multiple of what a lone expert could, without lowering the bar
• Human-in-the-loop by design: the AI proposes; a human owns the calls that matter — judgment stays with the expert
• Greenfield ownership: you own a whole problem end to end — a real workstream on a production platform serving enterprise silicon customers, not a demo