Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging

Amazon Inc.; Cupertino (CA); On-site; USD 177,000 - 247,000; Full time

Benefits offered by this job

Health insurance

RSUs

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs, within AWS, seeks a Package Layout Design Engineer to help design advanced IC packages for next‑gen ML and data center ASICs. You will perform die floor planning, RDL/substrate routing, and interposer work, coordinating with ASIC teams and OSAT partners to deliver robust layouts.

You will also ensure design rules, DFM compliance, and impedance/electrical constraint integration across multi‑layer substrates, with collaboration across SI/PI teams in a dynamic environment in

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Experience with debugging at multiple levels from IP to SoCs.
• Experience verifying across logic levels from IP to full system.

Responsibilities

• Execute package layout tasks across the design cycle including die floor planning and tape out release.
• Implement physical designs for 2.5D/3D-IC packaging and interposers.
• Support floorplan development with die placement, bump maps, and power/ground distribution.
• Perform RDL and substrate routing for high-density interconnects.
• Coordinate die-level RDL routing with ASIC teams for die-package interface.
• Contribute to cross-level layout co-optimization across die, interposer, and PCB levels.
• Maintain package stack-up definitions with SI/PI and materials teams.
• Run DRC and connectivity checks and support design closure.
• Refine design rules with OSAT partners and foundries for DFM compliance.
• Collaborate with SI/PI engineers to incorporate electrical constraints into layout.

Skills

IC package layout

Physical design

Debugging skills

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

RDL routing

Interposer/substrate knowledge

DFM constraints

Electrical constraints integration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or Communications Engineering

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.

Key job responsibilities

• Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
• Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan‑out wafer‑level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
• Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
• Perform RDL and substrate routing for high‑density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi‑layer organic substrates or silicon interposers.
• Support die‑level RDL routing and bump planning in coordination with ASIC physical design teams to help co‑optimize the die‑package interface.
• Contribute to cross‑level layout co‑optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
• Assist in maintaining package stack‑up definitions in collaboration with SI/PI and materials engineering teams.
• Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
• Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
• Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout — impedance‑controlled routing, power plane optimization, and critical net shielding.

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related field
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
• 5+ years of experience in IC package layout and physical design
• Experience executing package designs from concept through tape out for multi‑layer organic substrates or silicon interposers
• Hands‑on experience with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent
• Understanding of advanced packaging technologies: 2.5D/3D-IC, fan‑out WLP, RDL, TSV, microbump, or silicon bridge interconnects
• Working knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity checks)
• Experience with bump map and ball map definition, escape routing strategies, and power/ground plane design
• Good communication skills with the ability to work effectively across design, SI/PI, and manufacturing teams

Preferred Qualifications

• Master's degree in Electrical or Communications Engineering or a related field
• Experience with formal verification techniques including abstraction and end‑to‑end checking
• Experience with ARM and various DSP ISAs
• Experience with current and upcoming RF standards in cellular (4G/5G NR), WiMAX, 802.11ad, microwave backhaul, or related broadband wireless standards
• Experience with industry standard tools and scripting languages (Python or Perl) for automation
• MS with 3+ years in IC package layout and physical design
• Familiarity with substrate and interposer manufacturing processes, material properties, and their impact on design decisions
• Exposure to chiplet‑based or heterogeneous integration packaging architectures
• Familiarity with package‑level SI/PI concepts (impedance control, PDN layout, crosstalk‑aware routing) sufficient to collaborate with SI/PI engineers
• Experience developing automation scripts (Python, TCL, Skill, Ravel) for layout tasks or design rule checks
• Exposure to working with OSAT partners on NPI builds or yield improvement efforts
• Familiarity with high‑bandwidth memory (HBM) integration in advanced packaging contexts

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign‑on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits .

USA, AZ, Tempe - 153,600.00 - 215,000.00 USD annually

USA, CA, Cupertino - 176,600.00 - 247,300.00 USD annually

USA, TX, Austin - 153,600.00 - 215,000.00 USD annually