Package Design Engineer

Google Inc.; Sunnyvale (CA); On-site; USD 142,200 - 237,000; Full time

Job summary

Google Inc. is seeking a Chip Package Designer to develop substrate designs for advanced 2.5D/3.5D packaging of ML chips in Sunnyvale, CA. You will collaborate with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to optimize electrical performance and reliability.

You will manage all design phases, drive design reviews, and contribute to pursuing production-ready packaging solutions to maximize PPA and lower total cost of ownership.

Qualifications

• Bachelor's degree in Mechanical, Materials, Electrical, Technology, Science or related field, or equivalent experience.
• 8 years of chip package substrate design with Cadence APD or Mentor Expedition.
• Experience in substrate layout, design verification, DFM and tapeout for production.
• Experience in design automation and scripting.

Responsibilities

• Develop package substrate designs for advanced 2.5D/3.5D packaging for ML chips.
• Collaborate with SI/PI, Thermal/Mechanical, Assembly, and PCB teams to optimize electrical performance, reliability and assembly.
• Manage all design phases: routing feasibility, test vehicle creation, design reviews, artwork export and final documentation.
• Identify and incorporate advanced packaging technologies into Google chip design pipelines to improve PPA and power efficiency.
• Support production sign-off and cross-domain co-design initiatives across chip, package, and system levels.

Skills

Chip package substrate design

Cadence APD

Mentor Expedition

Scripting / design automation

Education

Bachelor's degree in engineering or related field

Master's or PhD in EE/CE/CS or related field

Tools

CAD for package drawings

Job description

corporate_fare Google place Sunnyvale, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
• 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
• Experience in chip package substrate layout, design verification, DFM and taping out for production.
• Experience in design automation and scripting.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience in working with cross functional teams including chip design, SI/PI, and PCB design teams.
• Experience in 2.5D/3.5D advanced package design.
• Experience in physical verification flow (LVS, DRC, connectivity).
• Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD).
• Ability to write scripts to customize elements of the Cadence or Mentor workflow.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance substrate designs, where your goal is to optimize package substrate design for electrical performance, reliability, and assembly.

You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, which contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance substrate designs, where your goal is to optimize package substrate design for electrical performance, reliability, and assembly.

You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, which contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Develop physical package substrate design of large form-factor package for ML high-performance computers (HPCs).
• Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity.
• Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
• Collaborate closely with signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
• Define and document the requirements for the package substrate design and bill of materials (BOM).

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.