NKI Kernel Expert - Trainium Performance & Migration

DigiNo; Northern (KY); Hybrid; USD 150,000 - 210,000; Full time

Job summary

DigiNo is seeking a specialized engineer to evaluate Neuron Kernel Interface (NKI) development tasks used to train and evaluate frontier AI models. You will assess CUDA→NKI migration fidelity, Trainium-specific performance, and cross-platform numerical correctness, delivering rubric-based feedback.

The ideal candidate has 2+ years of NKI kernel experience on AWS Trainium/Inferentia2, plus knowledge of tile-based computation, memory hierarchy management, and DMA orchestration, enabling concrete,

Qualifications

• 2+ years hands-on experience developing or optimizing kernels using the Neuron Kernel Interface (NKI) targeting AWS Trainium/Inferentia2 hardware
• Strong understanding of NKI-specific development patterns: tile-based computation, SBUF/PSUM/HBM memory-hierarchy management, partition-dimension constraints, and DMA orchestration
• Demonstrated experience assessing CUDA→NKI migration quality
• Familiarity with Trainium-specific performance profiling (NeuronCore pipeline utilization, tensor-engine throughput, memory-bandwidth bottlenecks)
• Experience defining or evaluating cross-platform numerical-correctness standards (GPU vs Trainium accumulation order, rounding behavior, mixed-precision semantics)

Skills

NKI kernel development

CUDA→NKI migration assessment

Trainium hardware knowledge

Memory hierarchy management

DMA orchestration

Cross-platform numerical correctness

Tools

AWS Neuron SDK

Neuron Compiler internals

Triton kernel development

Trainium benchmarking

Job description

DigiNo is seeking a specialized engineer to evaluate Neuron Kernel Interface (NKI) development tasks used to train and evaluate frontier AI models. You will assess CUDA→NKI migration fidelity, Trainium-specific performance, and cross-platform numerical correctness, delivering rubric-based feedback.

The ideal candidate has 2+ years of NKI kernel experience on AWS Trainium/Inferentia2, plus knowledge of tile-based computation, memory hierarchy management, and DMA orchestration, enabling concrete,