New Grad Compiler Engineer – MLIR, C++, AI Infra

SambaNova, Inc.; Austin (TX); Sur place; USD 131 000 - 197 000; Plein temps

Avantages offerts par ce poste

Equity

Health insurance

Headspace

Gympass+

One Medical

Employee Assistance Program

Résumé du poste

SambaNova is hiring a new grad Compiler Engineer to help build and optimize the compiler stack for the Reconfigurable Dataflow Unit (RDU). You will work on IR, lowerings, partitioning ML models, tensor tiling, and memory management, writing production code in C++ and Python, with mentorship from senior engineers.

You will collaborate with runtime and hardware teams to map operations onto the fabric, debug low-level issues, and gain exposure to AI accelerator architectures relevant for

Qualifications

• B.S. in Computer Science, Electrical Engineering, Computer Engineering, or related field.
• Experience in ML systems development, including ML compilers, LLM inference kernels, or kernel generation.
• Strong programming skills in Python and C/C++.
• Experience programming GPUs or other AI accelerators.

Responsabilités

• Implement and optimize passes in the compiler's IR and pass infrastructure.
• Lower and partition machine learning models for execution on the RDU.
• Develop tensor tiling and memory management for on-chip memory.
• Map operations onto the RDU fabric to improve model performance.
• Debug compiler and performance issues at a low level in C++ and Python.

Connaissances

Python

C/C++

ML systems development

GPU programming

Formation

B.S. in Computer Science or related field

Outils

MLIR

StableHLO

LLM kernel libraries

Description du poste

SambaNova is hiring a new grad Compiler Engineer to help build and optimize the compiler stack for the Reconfigurable Dataflow Unit (RDU). You will work on IR, lowerings, partitioning ML models, tensor tiling, and memory management, writing production code in C++ and Python, with mentorship from senior engineers.

You will collaborate with runtime and hardware teams to map operations onto the fabric, debug low-level issues, and gain exposure to AI accelerator architectures relevant for