Metrology Engineer - PIC Wafer Fab

NOKIA

Sunnyvale (CA)

On-site

USD 120,000 - 160,000

Full time

11 days ago

Get more replies from employers

Send a job-specific resume in minutes.

Job summary

Nokia's Photonic Integrated Circuit wafer fabs in Sunnyvale and San Jose develop and manufacture advanced InP semiconductor devices. The Metrology Engineer is responsible for sustaining and improving wafer fabrication processes through metrology, process characterization, defect analysis, and process control.

This role collaborates with Process Integration, Manufacturing, Equipment Engineering, and R&D teams to improve yield, product quality, and manufacturing performance.

Qualifications

  • BS/MS in EE, materials science, physics or related field.
  • 5+ years wafer fabrication experience; 7+ preferred.
  • Strong problem solving, data analysis and communication skills.
  • Experience with SPC, failure analysis and process characterization.
  • Hands-on with CD-SEM, profilometers, ellipsometers, defect inspection tools.

Responsibilities

  • Develop, qualify metrology recipes for CD-SEM, profilometry, overlay, ellipsometry, and defect inspection.
  • Own and support metrology equipment performance and improvements.
  • Develop metrology sampling plans and inline monitoring.
  • Analyze data to characterize processes and improve control.
  • Monitor SPC charts and RCCA-based excursions.
  • Support wafer-level failure analysis and external analyses.
  • Troubleshoot process and equipment with Operations and Eng.
  • Create equipment specs, procedures, OCAP docs.
  • Train operators/technicians on tools and procedures.
  • Support new tech development, qualifications, transfers, and ramp.

Skills

Metrology
Data analysis
SPC
Problem solving
Communication
Process improvement

Education

BS/MS in Electrical Engineering, Materials Science, Physics

Tools

CD-SEM
Profilometers
Ellipsometers
Defect inspection tools
MES systems

Job description

Nokia's Photonic Integrated Circuit (PIC) wafer fabs in Sunnyvale and San Jose develop and manufacture advanced Indium Phosphide (InP) semiconductor devices. The Metrology Engineer is responsible for sustaining and improving wafer fabrication processes through metrology, process characterization, defect analysis, and process control. This role works closely with Process Integration, Manufacturing, Equipment Engineering, and R&D teams to improve yield, product quality, and manufacturing performance.

Key Responsibilities
  • Develop, qualify, and maintain metrology recipes for CD-SEM, profilometry, overlay, ellipsometry, and defect inspection tools.
  • Own and support metrology equipment performance, qualification, and continuous improvement.
  • Develop metrology sampling plans and inline monitoring strategies.
  • Analyze process and metrology data to characterize processes and improve process control.
  • Monitor SPC charts and investigate process excursions using RCCA methodologies.
  • Support wafer-level failure analysis, including FIB, EDX, and coordination of external analyses.
  • Troubleshoot process and equipment issues in collaboration with Operations and Engineering teams.
  • Create equipment specifications, procedures, and OCAP documentation.
  • Train operators and technicians on metrology tools and procedures.
  • Support new technology development, process qualifications, technology transfers, and production ramp activities.
Qualifications
  • BS/MS in Electrical Engineering, Materials Science, Physics, or a related field.
  • 5+ years of semiconductor wafer fabrication experience (7+ preferred).
  • Strong problem-solving, data analysis, and communication skills.
  • Experience with statistical process control (SPC), failure analysis, and process characterization.
  • Hands-on experience with CD-SEM, profilometers, ellipsometers, and defect inspection tools preferred.
  • Experience with MES systems is a plus.
  • Experience in III‑V semiconductor technologies (InP or GaAs) is highly desirable.
  • Familiarity with photolithography, etch, deposition, and CVD processes preferred.
Work Schedule

Compressed work week: Monday-Wednesday and every other Thursday, 12‑hour day or night shifts.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Metrology Engineer - PIC Wafer Fab
Metrology Engineer - PIC Wafer Fab

NOKIA • San Jose (CA)

On-site
USD 120,000 - 180,000
Metrology Engineer – PIC Wafer Fab
Metrology Engineer – PIC Wafer Fab

Nokia • Sunnyvale (CA)

On-site
USD 140,000 - 190,000
Metrology Engineer – PIC Wafer Fab
Metrology Engineer – PIC Wafer Fab

Nokia • San Jose (CA)

On-site
USD 120,000 - 170,000
Metrology Engineer – PIC Wafer Fab
Metrology Engineer – PIC Wafer Fab

Nokia Corp. • Sunnyvale (CA)

Hybrid
USD 120,000 - 180,000
Metrology Engineer, PIC Wafer Fab (InP)
Metrology Engineer, PIC Wafer Fab (InP)

NOKIA • San Jose (CA)

On-site
USD 120,000 - 180,000
Metrology Engineer - PIC Wafer Fabrication & Yield
Metrology Engineer - PIC Wafer Fabrication & Yield

Nokia Corp. • Sunnyvale (CA)

Hybrid
USD 120,000 - 180,000
Metrology Engineer, PIC Wafer Fab - Data-Driven Process Improvement
Metrology Engineer, PIC Wafer Fab - Data-Driven Process Improvement

Nokia • San Jose (CA)

On-site
USD 120,000 - 170,000
Senior Metrology Engineer, PIC Wafer Fab (InP)
Senior Metrology Engineer, PIC Wafer Fab (InP)

NOKIA • Sunnyvale (CA)

On-site
USD 120,000 - 160,000
Senior Metrology Engineer – Semiconductor Process & Yield
Senior Metrology Engineer – Semiconductor Process & Yield

Nokia • Sunnyvale (CA)

On-site
USD 140,000 - 190,000
Wafer Fab Integration Engineering Technician (Weekday Day Shift)
Wafer Fab Integration Engineering Technician (Weekday Day Shift)

NOKIA • San Jose (CA)

On-site
USD 85,000 - 110,000