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Fintal Partners in New York seeks an experienced Hardware Machine Learning Engineer to deploy ML directly on custom hardware, including FPGA/ASIC paths. You will architect ML models with latency budgets and work across traders, researchers, and software engineers.
You will shape hardware roadmaps, translate model requirements into architectural decisions, and implement inference solutions from proof-of-concept through production with hardware teams.
A leading global trading firm is expanding its machine learning capabilities and looking for an experienced Hardware Machine Learning Engineer to help deploy ML directly onto custom hardware.
This firm builds its own hardware, software, and infrastructure in-house, so when a model hits a latency wall or a resource ceiling, the engineer doesn't file a ticket and wait, they go fix it. There's no vendor to wait on and no abstraction layer they're not allowed to touch. This is a rare opportunity to architect solutions from scratch, influence technical research direction, and see the work drive real impact in one of the most demanding computing environments in the world.
Exposure to ML compiler infrastructure such as MLIR, TVM, or XLA; a background in latency-sensitive or resource-constrained systems including high-frequency trading, particle physics data acquisition, or real-time signal processing; familiarity with functional verification methodologies such as SystemVerilog, UVM, or Cocotb.
Trading experience is a bonus, not a prerequisite. The firm is looking for researchers and engineers from any background who want to push the boundaries of what's computationally possible.