Senior Machine Learning Engineer

Fintal Partners; Chicago (IL); On-site; USD 140,000 - 200,000; Full time

Job summary

Fintal Partners is building next-generation ML infrastructure by deploying models on custom hardware. You will co-design ML models with researchers and engineers, balancing latency, precision, and resource use as core design considerations.

You will help shape the roadmap for custom hardware platforms, translating ML workloads into hardware decisions and partnering closely with hardware engineers to move from prototypes to production deployments.

Qualifications

• Deep understanding of hardware architectures for ML workloads.
• Experience mapping ML workloads to accelerators (FPGA/ASIC/other).
• Familiarity with ML frameworks (PyTorch, TensorFlow).
• Proficient in Python and C++.
• Strong collaboration across hardware, software, and research teams.

Responsibilities

• Co-design ML models with researchers and engineers while considering latency and precision constraints.
• Shape roadmap for custom hardware platforms translating ML workloads into architecture decisions.
• Work with hardware engineers to deploy ML inference solutions from research to production.
• Evaluate research on neural architecture search, quantization, ML systems, and hardware optimization.
• Drive performance optimization balancing accuracy with latency and throughput.

Skills

Hardware design awareness

Python

C++

Communication skills

ML fundamentals

Education

Master’s or PhD in EE/CS/Physics

Tools

VHDL

SystemVerilog

HLS

hls4ml

FINN

Vitis AI

Job description

Our client is building the next generation of machine learning infrastructure by deploying ML models directly onto custom hardware. This is a rare opportunity to help define an entirely new technology stack from the ground up architecting solutions from first principles, influencing long-term research direction, and seeing your work deployed in one of the world's most demanding compute environments.

Key Responsibilities

• Co-design machine learning models alongside researchers, engineers, and domain experts while treating hardware constraints such as latency, resource utilization, and numerical precision as core design considerations.
• Help shape the roadmap for custom hardware platforms by translating ML workloads into hardware architecture decisions.
• Partner closely with hardware engineers to implement, validate, and deploy ML inference solutions from research prototypes through production.
• Evaluate emerging research across neural architecture search, quantization, ML systems, and hardware-aware optimization, identifying innovations that can deliver measurable performance improvements.
• Drive performance optimization across both hardware and software, balancing model accuracy with strict latency and throughput requirements.

Required Qualifications

• Strong understanding of hardware architecture and the trade-offs involved in mapping machine learning workloads to FPGAs, ASICs, or other specialized accelerators.
• Experience with hardware development through technologies such as VHDL, SystemVerilog, High-Level Synthesis (HLS), or hardware deployment frameworks including hls4ml, FINN, or Vitis AI.
• Solid understanding of machine learning fundamentals, including neural network architectures, inference optimization, quantization techniques, and frameworks such as PyTorch or TensorFlow.
• Strong programming skills in Python, C++, or similar languages used for tooling, simulation, testing, and model development.
• Excellent communication skills with the ability to collaborate across multidisciplinary teams spanning hardware, software, and research.

Preferred Qualifications

• Experience with ML compiler technologies such as MLIR, TVM, XLA, or comparable compiler infrastructures.
• Background in performance-critical or resource-constrained systems, including high-frequency trading, real-time signal processing, particle physics, networking, telecommunications, or embedded systems.
• Familiarity with hardware verification methodologies such as UVM, Cocotb, or SystemVerilog verification environments.
• Master's or PhD in Electrical Engineering, Computer Science, Physics, or a related technical discipline, or equivalent industry experience.