Lead Vector Compute Architect

Bolt Graphics; Sunnyvale (CA); On-site; USD 180,000 - 220,000; Full time

Benefits offered by this job

Medical, Dental, & Vision - 100% cover

Equity - Stock Options

401(k) match

WFH Hardware

Job summary

Bolt Graphics in the Bay Area is seeking an experienced Lead Vector Compute Architect to define architecture for next-generation GPUs, focusing on data-parallel compute units and cross-functional collaboration across hardware, software, and system teams.

This on-site role drives architecture tradeoffs, system specifications, performance modeling, memory hierarchy, and post-silicon optimization while contributing to long-term technology roadmaps and product planning.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of experience in modern data-parallel microarchitecture.
• Experience with workload characterization, performance modeling, and data dependency control.
• Strong problem-solving, communication, and leadership skills.

Responsibilities

• Defined data-parallel microarchitectures satisfying ISA constraints.
• Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability.
• Develop and review system architecture specifications, interface definitions, and microarchitecture requirements.
• Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle.
• Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC- or similar modeling environments.
• Define memory hierarchy, coherency architecture, and cache structures.
• Work closely with verification teams to define architectural test plans and validation strategies.
• Support silicon bring-up, debug, performance tuning, and post-silicon optimization.
• Contribute to long-term technology and product roadmap planning.

Skills

Modern data-parallel microarchitectur

Subsystem integration

Workload characterization

Performance modeling

Out-of-order data dependency

Utilization / occupancy optimization

High-performance architecture design

RTL development

Architecture modeling tools

Firmware/software interaction in SoC

Leadership and communication

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

About the role:

We are looking for an experienced and highly motivatedLeadVector ComputeArchitect to lead the architecture definition and technical direction forBolt’snext-generationGPUs. The ideal candidate will have strongexpertiseindataparallelcomputeunitarchitecture development, performance modeling,data pathintegration, and cross-functional collaboration across hardware, software, and systemsteams.

This role involves defining scalable and high-performance architectures for advancedcomputeworkloadsincludinggraphics,HPC,andsystem management.This role is on-site and requires someone to be local to the Bay Area.

What you’ll do:

• DefinedataparallelmicroarchitecturesatisfyingISAconstraints.

• Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability.

• Develop and review system architecture specifications, interface definitions, and microarchitecture requirements.

• Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle.

• Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemCor similar modeling environments.

• Define memory hierarchy, coherency architecture, and cache structures.

• Work closely with verification teams to define architectural test plans and validation strategies.

• Support silicon bring-up, debug, performance tuning, and post-silicon optimization.

• Contribute to long-term technology and product roadmap planning.

Qualifications:

• Strong understanding of moderndataparallelmicroarchitectures and subsystem integration.

• Bachelor’s orMaster’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 6+ years of experience inmoderndataparallelmicroarchitectureincluding:

• Workload characterization and profiling
• Performance modeling
• Out-of-order data dependency and control
• Utilization / occupancy optimization
• High-performance architecture design technique s

Experience with one or more of the following:

• CPU/GPU/NPU architectures
• NoC/interconnect architectures
• Cache coherency protocols (CHI/ACE/CXL)
• High-speed interfaces (PCIe, UCIe, Ethernet)
• Memory systems (DDR, LPDDR, HBM, GDDR)
• Power,performance,andareaoptimization
• Strong knowledge of RTL development and verification methodologies.
• Experience with architecture modeling and performance analysis tools.
• Familiarity with firmware/software interaction in complex SoC systems.
• Excellent problem-solving, communication, and leadership skills.

Compensation Range:

$180,000–$220,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.

Benefits:

• Medical, Dental, & Vision - 100% covered premiums
• Equity - Stock Options
• 401(k) match
• WFH Hardware

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.