Hardware Engineering Manager

Bolt Graphics; Sunnyvale (CA); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

Medical, Dental, & Vision - 100% paid

Equity - Stock Options

401(k) match

WFH Hardware

Job summary

Bolt Graphics in Sunnyvale, CA, is seeking a Hardware Engineering Manager to own the product lifecycle and system-level deployment of the Zeus GPU platform, moving beyond legacy architectures.

You will bridge silicon, system hardware, and operations to deliver PCIe accelerator cards and 2U HPC servers, lead hardware definition, manage ODM/EMS, and drive the hardware ecosystem to displace traditional GPU clusters.

Qualifications

• 5+ years defining or engineering high-performance PCIe-based add-in cards (AIC) or complex server systems.
• Deep understanding of PCIe Gen 5.0/6.0 electrical integrity and signal routing.
• Memory architectures (DDR5, LPDDR5X, or HBM) and large memory scaling for FP64 simulations.
• Experience with embedded processors (RISC-V/ARM), Linux-based system architectures, and high-speed networking fabrics (400Gbps+).
• Experience taking hardware from tape-out to production.

Responsibilities

• Own the hardware roadmap and form-factor optimization for PCIe accelerator cards and 2U rack-mount servers.
• Collaborate with firmware and platform teams to ensure standalone Linux operation with BMC/IPMI.
• Lead cross-functional execution from tape-out through validation to mass production.
• Coordinate with ODMs and suppliers to optimize BOM and manufacturing resilience.

Skills

High-speed PCIe hardware

PCIe Gen 5/6

RISC-V familiarity

Embedded & networking fundamentals

Education

BS/MS in Electrical/Computer Engineering

MBA (valued)

Tools

RISC-V

Linux-based systems

BMC/IPMI

Job description

Hardware Engineering Manager

Bolt Graphics Sunnyvale, California, United States

About this position

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values

• Be Fearless: Unmute yourself. Test boundaries and get proven right.
• Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
• Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:

We are looking for a highly technical, execution-oriented Hardware Engineering Manager to own the product lifecycle and system-level deployment of our disruptiveZeus GPU platform. Moving past legacyarchitectures, Bolt Graphics is redefining high-performance computing, advanced physics simulation (FP64), and real-time path tracing with a ground-up RISC-V controlled architecture thatoperatesas a standalone computing system.

In this role, you will bridge the gap between silicon architecture, system hardware design, and operations to deliver two critical form factors to market: high-densityPCIe Gen 5/6 accelerator cardsfeaturing innovative user-expandable memory (LPDDR5X + DDR5 SO-DIMMs) and ultra-scalable2U HPC Server configurations. You will lead the hardware product definition, manage tier-1 ODM/EMS delivery, and drive the hardware ecosystemrequiredto displace legacy, power-hungry GPU clusters.

What you'll do:

Product Definition & Hardware Roadmap

FormFactor Optimization:Own the PRD and hardware requirements for single/dual-chiplet PCIe accelerator form factors (e.g., Zeus 1c26/2c26) and multi-chip 2U rack-mount server architectures.

Memory Subsystem Strategy:Drive product requirements around our unique, high-capacityexpandable memory subsystem, balancing the integration of on-board LPDDR5X with user-upgradable DDR5 SO-DIMM/DIMM slots to unlock up to 2.25TB per server node.

Native Network Integration:Define the roadmap for our integrated, high-bandwidth communication fabrics,utilizingnative400GbE / 800GbE interfacesbuilt directly into the accelerator toeliminatethe need for discrete NICs, loweringlatencyand TCO.

System Engineering & Infrastructure Co-Design

Standalone Subsystem Readiness:Collaborate with firmware and platform teams to ensure the embedded RISC-V control processor seamlessly runs standalone Linux subsystems, including server management features like integrated BMC and IPMI.

Thermal & Power Efficiency:Manage system trade-offs for highly efficient power targets (ranging from 120W single-slot boards up to 500W multi-chip server environments), ensuringoptimalbalance between air-cooled density and deployment in legacy data center infrastructures.

Execution, NPI & Operations Collaboration

Silicon-to-System Execution:Drive cross-functional execution from recent chip tape-out through hardware validation, system-level NPI, and mass production.

Supply Chain & Partner Engagement:Partner with hardware engineering, board layout, signal integrity teams, and ODMs to source components,optimizeBill of Materials (BOM) costs, and ensure manufacturing resilience for complex high-speed PCBs.

Qualifications:

Technical Competencies

High-Speed Hardware Architecture:5+ years of experience defining or engineering high-performance PCIe-based add-in cards (AIC) or complex server systems. Deep understanding ofPCIe Gen 5.0 / 6.0electrical integrity, form factor constraints, and signal routing.

Memory & System Topology:Strong technical literacy in memory architectures (DDR5, LPDDR5X, or HBM) and an understanding of how large memory capacity scales performance in FP64 scientific simulations (e.g., electromagnetic wave simulations) and path tracing.

Embedded & Networking Fundamentals:Familiarity with embedded processors (RISC-V/ARM), Linux-based system architectures, and network fabrics (Ethernet/InfiniBand)operatingat 400Gbps+.

Product Leadership & Execution

Startup Agility with Enterprise Rigor:Proven track record of taking complex silicon or hardware products from post-tape-out validation into full production.

TCO Optimization:Strong business acumen with the ability to build data-driven Total Cost of Ownership (TCO) models, proving the cost and power benefits of Bolt’s architecture against legacy, high-wattage hardware clusters.

Academic & Professional Background:BS/MS in Electrical Engineering, Computer Engineering, or a related hardware field. An MBA is highly valued to successfully bridge complex engineering milestones with customer commercialization strategy.

Preferred Qualifications

Direct experience working on high-performance compute accelerators, GPUs, or server motherboards designed forrenderfarms and HPC centers.Experience navigating the hardware ecosystem transition from x86/Arm host controllers to alternative open architectures likeRISC-V.Familiarity with the mechanical and thermal constraints of fitting high-density, multi-slot accelerator boards into standard data center rack infrastructure.

Compensation Range:

$200,000–$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.

Benefits:

• Medical, Dental, & Vision - 100% covered premiums
• Equity - Stock Options
• 401(k) match
• WFH Hardware

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.