Lead SoC DRAM Memory Validation Program Manager

Apple Inc.; Cupertino (CA); Hybrid; USD 175,000 - 312,000; Full time

Benefits offered by this job

Medical benefits

Stock programs

Relocation support

Job summary

Apple Inc. in Cupertino seeks a SoC DRAM Memory Subsystem Validation Engineering Program Manager to lead memory readiness for our custom SoCs.

You will drive bring-up, validation and complex debug across multi-functional teams, shaping the DRAM roadmap and coordinating with DRAM architecture and DV groups. The role interfaces with Memory Controller Design, DDR PHY, DRAM product engineering, and software teams to ensure high-quality silicon delivered to mass production, while meeting Apple’s

Qualifications

• BS + 10 years of relevant experience in SOC DRAM memory design, validation, architecture or test/product engineering.
• Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering.
• Strong debugging and leadership skills with ability to drive cross-functional teams.

Responsibilities

• Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware, and Software.
• Drive debug activities in post silicon environments, root-cause problems and steer the team to the best corrective action to move forward.
• Plan and lead adoption of DRAM technologies, custom package development and qualification process with multi-functional teams.
• Work closely with the DRAM GSM, DRAM & Package Engineering and SoC Program Management organizations to set priorities.
• Attend and drive technical sessions with DRAM vendors on new DRAM technology development to track and follow-up issues/action items and drive vendors to meet spec and schedule requirements.
• Work with DRAM GSM and silicon material management teams to plan and track distribution of new DRAM material across all systems in development.
• Enable tight collaboration between DFT, Product/Test/QA engineering, SiVal and Systems teams during NPI to finalize SoC performance targets and screen requirements.
• Drive internal program process to guarantee high quality silicon execution.

Skills

Debugging skills

Leadership

Technical communication

Cross-functional collaboration

Education

BS + 10 years of relevant experience

Tools

DDR PHY design

DRAM validation tools

SoC memory architecture

Job description

Apple Inc. in Cupertino seeks a SoC DRAM Memory Subsystem Validation Engineering Program Manager to lead memory readiness for our custom SoCs.

You will drive bring-up, validation and complex debug across multi-functional teams, shaping the DRAM roadmap and coordinating with DRAM architecture and DV groups. The role interfaces with Memory Controller Design, DDR PHY, DRAM product engineering, and software teams to ensure high-quality silicon delivered to mass production, while meeting Apple’s