Product Engineer (EMIR / PDN Analysis & Power Integrity)

Cadence Design Systems; San Jose (CA); On-site; USD 100,000 - 150,000; Full time

Job summary

Cadence Design Systems is seeking a product engineer specializing in Power Noise Reliability analysis. This position involves working with cutting-edge AI-driven methodologies while developing domain expertise and collaborating closely with R&D teams. Ideal candidates will possess robust experience in EMIR analysis and a strong technical background in digital design and debugging.

Qualifications

• 5+ years relevant industry experience in EMIR analysis, PDN analysis.
• Strong background in Digital logic Design, CMOS logic Design.
• Experience with 3DIC design and debugging skills required.

Responsibilities

• Be part of product team working on Power Noise Reliability analysis.
• Support strategic customers and functional product engineering.
• Develop methodologies and flows in the Multiphysics space.

Skills

Power Integrity

Debugging

TCL

Perl

Python

Education

Bachelor’s Degree in Electrical / Electronics / Electronics and Communication / VLSI Engineering

Master’s Degree

PhD

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities
• Be part of the product engineering team working on Power Noise Reliability analysis platform within Multiphysics Systems BU at Cadence.
• Build domain expertise in power integrity , 3DIC analysis & optimization , Industry’s first AI driven IR mitigation & fixing methodology , electrothermal optimization for digital designs.
• Work closely with R&D to facilitate the development of these methodologies and flows.
• Responsibilities also including supporting strategic customers and functional product engineering driving solutions in the Multiphysics space.

Qualifications
• Bachelor’s Degree in Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5 years related experience
• OR Masters with 2 - 3 years of related experience
• OR PhD with 0+ years of related experience

Experience and Technical Skills required
• 5+ years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation as designer or methodology/flow expert.
• Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design.
• Debugging of Low power and multiple power domain analysis for chip power integrity sign-off.
• Experience with 3DIC design and methodologies is a plus.
• Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.
• Ability to solve interface level problems emanating from IC Implementation side and System analysis side.
• Ability to debug Timing and thermal issues in relation to IR and EM is a plus.
• Knowledge on TCL, Perl or Python scripting.

Behavioral skills required
• Must possess strong written, verbal and presentation skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions.
• Work effectively across functions and geographies.
• Push to raise the bar while always operating with integrity.

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