Lead FPGA Architect for Low-Latency Trading

Radley James; New York (NY); On-site; USD 250,000 - 400,000; Full time

Job summary

Radley James is seeking a Senior FPGA Engineer to design and build a low-latency FPGA platform from first principles, collaborating with quantitative researchers, traders and software engineers in New York City. You will own architecture decisions and drive full lifecycle projects from concept to production, setting standards as the FPGA capability expands.

Compensation ranges from $250K to $400K base, with significant performance bonuses.

Qualifications

• Degree in Computer Science, Electrical Engineering or a related technical discipline.
• Significant hands-on FPGA engineering experience.
• Strong communication skills and the ability to collaborate with quantitative and software teams.

Responsibilities

• Design and build a low-latency FPGA platform from first principles.
• Develop FPGA solutions for electronic trading and market-data processing.
• Work with traders and researchers to identify opportunities for hardware acceleration.
• Own architecture and technical decisions across the FPGA environment.
• Integrate FPGA technology into the wider trading and research stack.
• Lead projects from concept through production lifecycle.
• Establish engineering standards and best practices as the FPGA capability grows.

Skills

FPGA engineering

SystemVerilog

VHDL

Low-latency design

Architectural decisions

Collaboration

Education

BS in CS/EE or related field

Tools

Vivado

Quartus

Job description

Radley James is seeking a Senior FPGA Engineer to design and build a low-latency FPGA platform from first principles, collaborating with quantitative researchers, traders and software engineers in New York City. You will own architecture decisions and drive full lifecycle projects from concept to production, setting standards as the FPGA capability expands.

Compensation ranges from $250K to $400K base, with significant performance bonuses.