Lead ESD Design Engineer for FinFET & SoC

Renesas; Chandler (AZ); On-site; USD 180,000 - 240,000; Full time

Job summary

Renesas is seeking an accomplished ESD expert to drive ESD methodology, IP development, and sign-off verification for advanced semiconductor products. You will lead design and validation across FinFET and high-speed interfaces.

You will collaborate with global teams and external partners to advance ESD robustness, develop automated verification flows, and mentor engineering staff while delivering results on aggressive schedules.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 10+ years of semiconductor ESD design experience.
• Strong knowledge of ESD device physics, HBM, CDM, TLP, VF-TLP, Latch-Up, and FinFET technologies.
• Hands-on ESD protection design for FinFET SoCs and SerDes products.
• Experience with ESD cell design and custom ESD IP development.
• Experience with ESD sign-off methodologies and verification techniques.
• Experience with Calibre PERC or equivalent ESD verification tools.
• Ability to drive across multiple product families and tech nodes.
• Demonstrated leadership in cross-functional engineering environments.
• Strong initiative, collaboration, ownership, and ability to meet aggressive timelines.
• Strong technical writing skills for reports, design reviews, and recommendations.
• Strong communication of risks and methodologies across global teams (Japan, Europe, Asia).

Responsibilities

• Design and optimize custom ESD protection devices, clamps, and ESD IP solutions.
• Provide co-design support to maximize performance and ESD protection robustness.
• Lead ESD sign-off reviews and risk assessments for complex SoCs and mixed-signal products.
• Develop and maintain automated ESD verification methodologies and flows.
• Support silicon characterization using HBM, CDM, TLP, VF-TLP, and Latch-Up testing.
• Drive root-cause analysis of ESD-related failures and implement corrective actions.
• Collaborate with foundries, EDA vendors, and internal design teams.

Skills

ESD design expertise

Leadership

Cross-functional collaboration

Technical writing

Communication skills

Education

M.S. or Ph.D. in Electrical Engineering or related field

Tools

Calibre PERC

ESD verification tools

Job description

Renesas is seeking an accomplished ESD expert to drive ESD methodology, IP development, and sign-off verification for advanced semiconductor products. You will lead design and validation across FinFET and high-speed interfaces.

You will collaborate with global teams and external partners to advance ESD robustness, develop automated verification flows, and mentor engineering staff while delivering results on aggressive schedules.