Lead ESD Architect for FinFET SoCs & IP

Renesas Electronics; Chandler (AZ); On-site; USD 170,000 - 210,000; Full time

Job summary

Renesas Electronics seeks an experienced ESD expert to drive ESD methodology, IP development and sign-off for advanced semiconductor products, including FinFET technologies and high-speed interfaces. You will design and optimize ESD protection devices and IP, leading sign-off reviews, and developing automated verification flows for multiple product families and technology nodes.

Collaborating with foundries, EDA vendors, and internal teams, you will perform root-cause analysis of ESD failures

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 10+ years of semiconductor ESD design experience.
• Strong knowledge of ESD device physics, HBM, CDM, TLP, VF-TLP, Latch-Up, Advanced CMOS and FinFET technologies.
• Hands-on experience with ESD protection design for FinFET SoCs and SerDes products.
• Hands-on experience in ESD cell design and custom ESD IP development.
• Strong knowledge of ESD sign-off methodologies and verification techniques.
• Experience with Calibre PERC or equivalent ESD verification tools.
• Proven ability to develop and deploy ESD methodologies across multiple product families and technology nodes.
• Demonstrated leadership experience in complex cross-functional engineering environments.
• Strong initiative, collaboration, and ownership, with a proven track record of driving results under aggressive timelines.
• Strong technical writing skills with the ability to produce clear technical reports, design reviews, and engineering recommendations.
• Strong communication skills with the ability to communicate technical risks and methodologies across global teams.

Responsibilities

• Design and optimize custom ESD protection devices, clamps, and ESD IP solutions.
• Provide co-design support to maximize performance and ESD protection robustness.
• Lead ESD sign-off reviews and risk assessments for complex SoCs and mixed-signal products.
• Develop and maintain automated ESD verification methodologies and flows.
• Support silicon characterization using HBM, CDM, TLP, VF-TLP, and Latch-Up testing.
• Drive root-cause analysis of ESD-related failures and implement corrective actions.
• Collaborate with foundries, EDA vendors, and internal design teams.

Skills

ESD design

HBM

CDM

TLP

VF-TLP

Latch-Up

FinFET

SoC sign-off

SerDes

Calibre PERC

Education

MS or PhD in Electrical Engineering

Tools

Calibre PERC

Job description

Renesas Electronics seeks an experienced ESD expert to drive ESD methodology, IP development and sign-off for advanced semiconductor products, including FinFET technologies and high-speed interfaces. You will design and optimize ESD protection devices and IP, leading sign-off reviews, and developing automated verification flows for multiple product families and technology nodes.

Collaborating with foundries, EDA vendors, and internal teams, you will perform root-cause analysis of ESD failures