Lead ASIC Engineer

BioTalent; San Diego (CA); On-site; USD 130,000 - 180,000; Full time

Job summary

BioTalent in San Diego seeks a seasoned chip-design professional to own requirements, oversee external partner work, and drive silicon qualification. You will lead reviews from architecture through sign-off, ensuring designs meet specifications and are ready for fabrication.

Ideal candidates have 5+ years in ASIC/SoC, with analog or mixed-signal IC design or verification experience, and a track record in SPICE/Cadence reviews, DRC/LVS, and DFT. Medical device experience is a plus.

Qualifications

• BS/MS in Electrical Engineering or related field with IC design focus.
• 5+ years of ASIC or SoC experience, including at least one chip from concept to silicon.
• Analog or mixed-signal IC design or verification background.
• Experience reviewing simulation results (SPICE/Cadence), physical verification (DRC/LVS) and DFT.
• Experience managing an outside design partner, foundry or fab.
• Bonus: medical device experience or implantable electronics.

Responsibilities

• Write and maintain chip requirements and specifications with full traceability.
• Lead technical reviews with the design partner from architecture through final sign-off.
• Evaluate simulation, physical verification and design-for-test work, and decide on fabrication.
• Identify and manage technical risks such as noise, power, matching and process variation across a large channel count.
• Work with the in-house test engineer on silicon bring-up and characterization, and lead debug when issues come up.
• Drive any required design revisions and the plan to re-verify them.
• Support the chip through qualification and production, and define requirements for future generations.

Skills

ASIC/SoC experience

Analog/mixed-signal IC design

DFT verification background

Simulation review (SPICE/Cadence)

Outsourcing/partner management

Medical device experience (bonus)

Education

B.S./M.S. in Electrical Engineering or related field (IC design focus)

Tools

SPICE/Cadence

DRC/LVS

DFT tools

Job description

POSITION SUMMARY

You won’t be designing the chip yourself. You’ll define what it needs to do, scrutinize the partner’s work at every stage, and decide when it’s ready for fabrication. When silicon comes back, you’ll lead the effort to confirm it performs as intended and get to the bottom of anything that doesn’t.

RESPONSIBILITIES

• Write and maintain the chip requirements and specification, with full traceability
• Lead technical reviews with the design partner from architecture through final sign-off, digging into the underlying schematics and simulation data
• Evaluate simulation, physical verification and design-for-test work, and own the decision to proceed to fabrication
• Identify and manage technical risks such as noise, power, matching and process variation across a large channel count
• Work with the in-house test engineer on silicon bring-up and characterization, and lead debug when issues come up
• Drive any required design revisions and the plan to re-verify them
• Support the chip through qualification and production, and define requirements for future generations

QUALIFICATIONS

• BS or MS in Electrical Engineering or related field, with a focus on IC design
• 5+ years of ASIC or SoC experience, including at least one chip taken from concept through silicon
• An analog or mixed-signal IC design or verification background
• Experience reviewing simulation results (SPICE/Cadence), physical verification (DRC/LVS) and DFT
• Experience managing an outside design partner, foundry or fab
• Bonus: medical device experience (design controls, FDA submissions) or implantable electronics