Lead Architect, SoC

SambaNova; Palo Alto (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

An innovative company is seeking a Lead Architect for SoC to drive the architectural evolution of AI infrastructure. In this pivotal role, you will design and architect memory performance solutions, ensuring the seamless integration of cutting-edge technologies that power advanced AI workloads. Collaborating with a talented team, you will define specifications for network-on-chip and memory subsystems while mentoring junior engineers. This is an exciting opportunity to contribute to groundbreaking innovations in AI and HPC, where your leadership and expertise will have a direct impact on the company's success. If you are passionate about high-performance distributed systems, we want to hear from you!

Benefits

Cutting-edge technologies

Collaborative environment

Impact on company success

Work with industry leaders

Qualifications

• 10+ years of experience in ASIC design with a strong focus on ML and CPU/GPU architecture.
• Proven leadership skills and ability to mentor junior engineers.

Responsibilities

• Define NoC and memory subsystem architecture specifications.
• Lead execution of NoC and memory subsystems for performance and functional closure.

Skills

ASIC design

Machine Learning architecture

Network-on-Chip (NoC) design

Memory subsystem architecture

Technical leadership

Communication skills

Education

Bachelor's degree in Electrical Engineering and Computer Science

Master's degree in Electrical Engineering and Computer Science

Tools

Performance simulators

Job description

We’re seeking a Lead Architect, SoC to join our talented HW team—a group of engineers who have a proven track record of building software that directly powers advanced AI workloads and scientific computing. As a key technical leader, you will be responsible for designing and architecting our end to end memory performance and solution.

Roles and Responsibilities

• Define the network-on-chip (NoC) and memory subsystem architecture specifications.
• Conduct value, feasibility, and cost studies to define the feature set.
• Design a performant, reliable, and user-friendly NoC and memory microarchitecture.
• Collaborate with silicon / system / SW teams to ensure cross-functional convergence of architecture.
• Lead the execution of NoC and memory subsystems to achieve functional, performance, and PPA closure.
• Work with compiler and runtime software teams to enhance cross-functional ML model performance.
• Mentor and lead junior engineers.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering and Computer Science (EECS) with 10+ years (or equivalent) of experience in ASIC design.
• Deep understanding of the architecture of ML accelerators or CPUs/GPUs.
• Extensive knowledge of NoC protocols and topologies, memory address space, QoS, and DMA.
• Proven track record of delivering high bandwidth and low latency in multi-agent network-on-chip designs.
• Strong hands-on experience in authoring architecture and microarchitecture specifications.
• Technical or team leadership experience.
• Highly motivated, independent, organized, and strong communication skills.

Preferred Qualifications

• Master’s degree in EECS with 15+ years of experience in ASIC design.
• Ability to extract feature requirements from workloads, such as ML models.
• Proven silicon track record of successful full-cycle development from planning to product.
• Experience with performance simulators.
• Solid understanding of machine learning models.
• Knowledge of compilers and runtime software stacks.

What We Offer:

• Opportunity to work on cutting-edge technologies that power the next generation of AI and ML applications.
• A collaborative, dynamic environment where your ideas and leadership will have a direct impact on the success of the company.
• A chance to work with some of the brightest minds in the industry and contribute to groundbreaking innovations in AI, HPC, and distributed computing.

If you're passionate about designing high-performance, distributed systems and want to lead the architectural evolution of AI infrastructure, we want to hear from you.