Lead AI Accelerator Performance Architect

Morr0; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Morr0 is seeking a Principal Performance Modeling Architect in the Bay Area (onsite). You will own the performance analysis framework used to evaluate proposed silicon and system architectures before they are built.

You'll collaborate with senior GPU/AI architects to shape accelerator compute, memory, interconnect, and cluster-level systems, developing production-quality modeling tools in Python and C++. This hands-on IC role will influence RTL decisions and architecture choices, ensuring

Qualifications

• Experience in GPU/TPU/NPU performance modeling.
• Background in architecture simulation or analytical modeling for AI accelerators.
• Experience with LLM training/inference performance.
• Knowledge of memory hierarchy and bandwidth modeling.
• Familiarity with NoC, fabric, and interconnect performance.
• Experience with Python and C++ modeling frameworks.
• Understanding roofline and bottleneck analysis.

Responsibilities

• Build end-to-end performance models for AI accelerator platforms.
• Model workloads across silicon, memory, interconnect, and multi-accelerator systems.
• Translate proposals into projections of performance, power, and cost.
• Identify bottlenecks and quantify architectural trade-offs before RTL/silicon.
• Model LLM inference workloads including batching and KV-cache management.
• Develop production-quality analytical frameworks in Python/C++.

Skills

Performance modeling

GPU/TPU/NPU modeling

Architecture analysis

LLM inference performance

System-level optimization

Tools

Python

C++

Job description

Morr0 is seeking a Principal Performance Modeling Architect in the Bay Area (onsite). You will own the performance analysis framework used to evaluate proposed silicon and system architectures before they are built.

You'll collaborate with senior GPU/AI architects to shape accelerator compute, memory, interconnect, and cluster-level systems, developing production-quality modeling tools in Python and C++. This hands-on IC role will influence RTL decisions and architecture choices, ensuring