IP Design Engineer

ObjectWin Technology; Santa Clara (CA); Remote; USD 120,000 - 160,000; Full time

Job summary

A leading technology firm is seeking an experienced digital designer for a remote position focused on soft IP development for FPGA's using Verilog/Systemverilog. The ideal candidate has 7 to 12 years of experience and a strong background in digital design and RTL development. Responsibilities include integrating third-party IP cores and working with verification engineers to ensure design reliability. This role offers an opportunity to work with cutting-edge technology in a fully remote setting.

Qualifications

• 7 to 12 years of experience in digital design.
• Proven RTL coding experience using Verilog and/or System Verilog.
• Strong knowledge in digital design and microarchitecture.

Responsibilities

• Develop soft IP for FPGA's using Verilog/Systemverilog.
• Integrate third-party IP cores into FPGA systems.
• Collaborate with verification engineers to debug issues.

Skills

Digital design

Verilog/Systemverilog

FPGA integration

RTL development

Video domain experience

Tools

Xilinx Vivado

Job description

Position is 100% remote
Interview process is with MS Teams

JOB DUTIES:

1. Soft IP Development for FPGA's using Verilog/Systemverilog.
2. Integrate third party IP cores into an FPGA system, create custom RTL wrappers for third party cores, and interface with IP vendors
2. Work with Verification Engineers to verify IP and debug issues.
3. Participate in board bring up as well as system level integration.

EXPERIENCE AND EDUCATION:

• 7 to 12 years of experience in digital design
• RTL coding experience using Verilog and/or System Verilog
• Strong in digital design, micro architecture , RTL development
• Working experience of AMD/Xilinx FPGA and Vivado
• Experience in Video domain (DisplayPort/MIPI/HDMI/SDI) is preferred
• Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces IPs/Solutions
• Good understanding of system design aspects and its impact on performance and throughput