Intern, Physical Design & DFT

Tenstorrent University Jobs; Austin, Boston, Fort Collins, Santa Clara (TX, MA, CO, CA); In loco; USD 69.000 - 96.000; Part-time

Descrizione del lavoro

Tenstorrent is seeking interns for on-site roles in Austin, TX (and other US locations) across Physical Design and DFT teams. You will tackle Synthesis, floorplanning, place & route, and JTAG/MBIST workstreams, matching to a team and location that fits best.

Ideal candidates are pursuing BS/MS/PhD in Electrical/Computer Engineering or CS, with a strong grasp of VLSI concepts, logic design, scripting in Python, and interest in AI-assisted design tools.

Competenze

• Hands-on experience with a commercial PnR toolchain (Synopsys, Cadence).
• Coursework or projects in DFT, test methodology, VLSI or digital design, computer architecture.
• Interest or exposure with AI tools to accelerate development and workflows.

Mansioni

• Synthesis, floorplanning, place & route, clocking, timing closure.
• Advanced Physical Design: ML-assisted design flows.
• DFT: Design hardware to enable structural post-silicon test (JTAG, MBIST, Scan/ATP).
• Gain hands-on experience in Design-for-Testability (DFT) to enable efficient testing.

Conoscenze

VLSI concepts

Scripting: Python

JTAG/MBIST knowledge

Logic design fundamentals

Power optimization

Formazione

BS in Electrical/Computer Engineering

MS/PhD preferred

Strumenti

Synopsys Cadence

DFT tools

JTAG/MBIST tooling

Descrizione del lavoro

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Overview: This is where verified RTL becomes an actual, manufacturable chip. Every timing constraint, every power tradeoff, every Design For Test (DFT) decision here determines whether the silicon works when it comes back from the fab.

What you might work on: This posting spans multiple teams within Physical Design and DFT. One application, one recruiter screen — then we match you to the specific team and location that fits best. Team include:

• Physical Design: Synthesis, floorplanning, place & route, clocking, timing closure.
• Advanced Physical Design: ML-assisted approaches to physical design flows.
• DFT: Design hardware to enable structural post-silicon test. JTAG, Scan/ATPG, MBIST.

This role ison-site, based out of Austin, TX or Boston, MA or Fort Collins, CO or Santa Clara, CA.

Who You Are

• Currently pursuing a BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, Software Engineering.
• Solid understanding of logic design, VLSI, and transistor-level concepts.
• Familiarity with PnR tools, timing analysis, and power optimization techniques.
• Familiarity with JTAG, MBIST, and scan concepts.
• Comfortable scripting in Tcl, Perl, Shell, or Python.

What We Need

• Hands-on experience with a commercial PnR toolchain (Synopsys, Cadence).
• Coursework or projects in DFT, test methodology, VLSI or digital design, computer architecture.
• Interest or exposure with AI tools to accelerate development and workflows.

What You Will Learn

• The physical design flow, from RTL handoff to final tapeout.
• Timing, power, EM/IR, and area tradeoffs at the chip level.
• Industry-standard EDA tools and flows used in modern chip development.
• Gain hands-on experience in Design-for-Testability (DFT) to enable efficient testing.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Tenstorrent University Jobs’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.