Intern, ASIC Design

Ayar Labs; San Jose (CA); Presencial; USD 69.000 - 83.000; Jornada completa

Descripción de la vacante

Ayar Labs is offering an on-site internship in San Jose, CA, for an ASIC Design intern. The role targets advancing RTL design through AI-enabled flows, with emphasis on integration into existing tools and verification steps.

Candidates should be pursuing a Master’s in Electrical Engineering and have hands-on experience with RTL, Verilog/SystemVerilog, and Python. The program runs May–August 2027 and is based in the San Jose office.

Formación

• Experience with RTL design and hardware description languages.
• Programming in Python for flow automation and testing.
• Familiarity with Verilog/SystemVerilog is required.

Responsabilidades

• Assist in developing an AI-enabled flow to accelerate RTL design and verification.
• Integrate new flow with Ayar Labs’ existing design tools and processes.

Conocimientos

RTL Design

Verilog/SystemVerilog

Python

Educación

Master's in Electrical Engineering

Descripción del empleo

Intern, ASIC Design

Term: May to August 2027

Please note:

• Position location is on-site in San Jose Office
• There is no immigration (except F1) or relocation support for this position
• Posting expires upon application threshold

Position Description

Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. In this internship, you will help develop an AI flow to accelerate RTL design, including microarchitecture implementation, component integration, and functionality checking. The flow should integrate seamlessly with existing design tools and AI-enabled flows currently in use at Ayar Labs.

Intern Skillset Needed

• Experience in : RTL Design, Verilog/SystemVerilog, Python

Education Requirements

• Candidate should be actively pursuing a Master’s Degree in Electrical Engineering

Pay Range: $50 - 60/hourly, depending on education level

Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.