Infinity Fabric Performance Engineer

AMD; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD in Austin, TX seeks a Performance Engineer for the Infinity Fabric Architecture to define and deliver high‑performance memory interconnects. You will lead RTL perf analysis and verification for the fabric interconnect, collaborating with architecture, design and modeling teams on state‑of‑the‑art SoC memory systems.

You will drive performance debug across IP and SoC levels in simulation and emulation, develop benchmarks, and advance debugging tooling.

Qualifications

• Experience in RTL performance analysis and debug using hardware simulation or emulation.
• Hands-on with simulation testbench bring-up and new performance test cases.
• System-level performance debug across CPU/GPU/I/O workloads.
• Deep memory system and interconnect design knowledge.
• Proficient in Verilog/SystemVerilog; coding in C/C++ plus scripting.

Responsibilities

• Perform RTL performance analysis and verification for Infinity Fabric Interconnect.
• Provide technical leadership with architecture, design and modeling teams on high-performance SoC memory systems.
• Execute performance verification plans at IP level; support SoC-level performance debug in simulation and emulation.
• Analyze memory system optimizations; develop and run benchmarks in sim/emu environments.
• Debug performance failures; identify bottlenecks; propose RTL/data-driven solutions.
• Enhance debug infrastructure, tooling, and visualization for faster analysis.
• Leverage AI-based tools to improve productivity and workflows.

Skills

RTL perf analysis

Hardware simulation

SystemVerilog

Verilog

C/C++

Python/Perl scripting

Performance debugging

Benchmarking

Debug infrastructure

Data analysis

Technical presentation

Memory system architecture

Education

BS, MS, or PhD in Electrical or Computer Engineering

Tools

Simulation/Emulation platforms

Debug tooling

Job description

AMD in Austin, TX seeks a Performance Engineer for the Infinity Fabric Architecture to define and deliver high‑performance memory interconnects. You will lead RTL perf analysis and verification for the fabric interconnect, collaborating with architecture, design and modeling teams on state‑of‑the‑art SoC memory systems.

You will drive performance debug across IP and SoC levels in simulation and emulation, develop benchmarks, and advance debugging tooling.