IC Package Engineer Cupertino, CA

Etched.ai, Inc.; Mississippi; On-site; USD 90,000 - 150,000; Full time

Job summary

Join a pioneering team focused on developing AI-specific hardware in Cupertino. As an IC Package Design Engineer, you will lead the design of advanced packaging solutions that enhance the performance of AI chips. Your expertise in CoWoS and large-scale BGA designs will be crucial in ensuring the integrity of the next generation of AI hardware. This role offers a collaborative environment where engineering meets research, allowing you to make significant contributions to groundbreaking projects. With competitive perks and a supportive team, this is an opportunity to thrive in a forward-thinking company dedicated to innovation.

Benefits

Full medical, dental, and vision packages

Housing subsidy of $2,000/month

Daily lunch and dinner

Relocation support

Qualifications

• 5+ years in advanced IC package design with CoWoS or equivalent technologies.
• Strong understanding of package warpage and coplanarity challenges.

Responsibilities

• Drive end-to-end package design process, collaborating with teams and vendors.
• Conduct mechanical analysis to minimize thermal and mechanical stress.

Skills

IC Package Design

CoWoS Technology

BGA Design

Mechanical Stress Analysis

Thermal Management Techniques

Package Design Tools (Cadence, Mentor)

Communication Skills

Education

Bachelor’s or Master’s in Electrical Engineering

Related Discipline

Tools

Cadence APD/SIP

Mentor Xpedition

Job description

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive experience with advanced packaging technologies such as CoWoS, large-scale BGA designs, and package warpage mitigation strategies. You will play a key role in ensuring the mechanical and electrical integrity of packages that power the next generation of AI hardware.

Representative Projects:

• Own the end-to-end package design process, including substrate layout and IC package design, while collaborating with internal teams and external vendors to deliver optimized, manufacturable solutions.
• Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating stiffeners as needed.
• Expertise in large-scale BGA design, including experience with packages exceeding 4000-ball arrays, ball pitch optimization, routing, and power/ground plane design.
• Conduct mechanical and warpage analysis to address package warpage and coplanarity requirements across varying package sizes, collaborating with mechanical teams for simulation and testing to minimize thermal and mechanical stress.
• Perform design validation by assessing package layouts against electrical and mechanical constraints, providing design reviews and guidance on substrate and interconnect solutions, while archiving DFM-related learning for continuous improvement opportunities.
• Collaborate cross-functionally with chip design, thermal, mechanical, and manufacturing teams to ensure holistic package solutions, while interfacing with vendors to align design requirements and production feasibility.
• Oversee package reliability testing, including thermal, warpage, shock, shear, HTSL, HAST, ALT, JESD22, and electrical tests, while interfacing with various vendors to ensure compliance and quality.

You may be a good fit if you have:

• Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, or related discipline.
• 5+ years of experience in advanced IC package design, including CoWoS or equivalent technologies.
• Proven experience in substrate layout and BGA package design for large ball arrays (>4000 balls) with >20Ghz signaling and >500W.
• Strong understanding of stiffener design, open vs. closed package requirements, and package warpage and coplanarity challenges across various sizes.
• Proficiency in package design tools such as Cadence APD/SIP, Mentor Xpedition, or similar.
• Familiarity with mechanical stress analysis, simulation, and validation methodologies.
• Solid communication skills to work across multi-disciplinary teams and external partners.
• Experience with advanced packaging nodes (e.g., 2.5D/3D stacking).
• Knowledge of thermal management techniques in package design.
• Previous experience working in AI, HPC, or semiconductor design companies.

We encourage you to apply even if you do not believe you meet every single qualification.

How we’re different:

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

• Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents.
• Housing subsidy of $2,000/month for those living within walking distance of the office.
• Daily lunch and dinner in our office.
• Relocation support for those moving to Cupertino.

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