IC Package Design Engineer

Advanced Technology Search; San Jose, Fort Collins (CA, CO); On-site; USD 100,000 - 150,000; Full time

Job summary

An innovative firm is on the lookout for a seasoned package design engineer to join their global R&D team. This role focuses on developing cutting-edge ASIC package designs for high-performance applications in artificial intelligence, networking, and 5G technologies. You'll be responsible for driving the design process, ensuring signal and power integrity, and collaborating with a talented team across various time zones. With a commitment to efficiency and quality, this position offers a unique opportunity to contribute to groundbreaking projects that shape the future of technology.

Qualifications

• 8+ years in flip-chip-BGA package design with high-speed SerDes.
• Strong knowledge of package-level signal and power integrity.

Responsibilities

• Design ASIC package layouts focusing on signal and power integrity.
• Manage multiple projects while ensuring manufacturability and reliability.

Skills

Flip-Chip BGA Package Design

Signal Integrity

Power Integrity

Project Management

Cadence APD

Self-Management

Education

BSEE or MSEE

Tools

Cadence APD

Job description

Job Description:

Company is seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5, and more. You’ll have the opportunity to collaborate with the team to create the package structures needed to enable new designs, and contribute to efficiency improvements for our design team.

Responsibilities:

1. Overall design responsibility for ASIC package designs and layout, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
2. 2 or more years experience with Cadence APD, SiP, or equivalent package layout CAD tool (3 or more years preferred).
3. Package design of critical structures for SerDes, ADC/DAC, DDR, etc.
4. Schedule, prioritize, and track your work across 2+ projects simultaneously.
5. General flip-chip BGA package design and engineering.
6. Project management and customer interface for your design projects.
7. Contribute to efficiency improvements for the design group.

Education, Experience & Requirements:

1. BSEE or similar field with 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes, or MSEE or similar field with 6+ years’ experience.
2. Knowledge of package-level signal integrity and power integrity, applicable to package designs.
3. Cadence APD (Allegro Package Designer) experience preferred; equivalent tools are acceptable.
4. Ability to cooperate with our worldwide team across multiple time zones, including co-design with internal team members and external (vendor) designers.
5. Strong self-management and organizational skills.