IC Layout Design Intern: Build Analog Circuits

Texas Instruments Incorporated; Dallas (TX); On-site; USD 34,000 - 48,000; Full time

Job summary

Texas Instruments Incorporated is seeking a Layout Design Intern to contribute to the creation and management of IC layouts from start to finish. You will floorplan, design, implement and verify analog ICs using CAD software, collaborating with global teams to meet precision, speed, area, and power targets.

You will support design engineers and ensure proper data for fab hand-off, documentation, and archive. A minimum GPA of 3.0 and progress toward an Electrical Engineering degree are required.

Qualifications

• Pursuing an Associate or Bachelors in Electrical Engineering or related field.
• GPA 3.0/4.0 minimum.
• Familiarity with electrical concepts (resistance, capacitance, voltage, current).

Responsibilities

• Collaborate with analog and digital design teams and the layout community.
• Floorplan, design, implement and verify analog IC layouts.
• Ensure layouts meet DRC/ERC rules and are robust and area-efficient.
• Prepare data for fab hand-off and documentation.
• Participate in layout reviews and create flow automation.

Skills

Layout design

Semiconductor basics

Team collaboration

Education

Associate's or Bachelor's in Electrical Engineering

Tools

Cadence Virtuoso

Assura LVS/DRC

Job description

Texas Instruments Incorporated is seeking a Layout Design Intern to contribute to the creation and management of IC layouts from start to finish. You will floorplan, design, implement and verify analog ICs using CAD software, collaborating with global teams to meet precision, speed, area, and power targets.

You will support design engineers and ensure proper data for fab hand-off, documentation, and archive. A minimum GPA of 3.0 and progress toward an Electrical Engineering degree are required.