High-Speed Digital Design Engineer — DDR, PCIe, Ethernet SI

Socket.dev; Redmond (WA); On-site; USD 136,000 - 184,000; Full time

Benefits offered by this job

401(k) matching

Health insurance

RSUs

Paid time off

Job summary

Amazon LEO is seeking a High Speed Digital Design Engineer in Redmond to own high-speed interfaces (DDR, Ethernet, SerDes) for next‑gen terminal products. You will drive component selection, schematic capture, and signal integrity validation across hardware, silicon, and systems teams to deliver robust, cost‑optimized designs for high‑volume manufacturing.

Responsibilities include channel modeling, SI/PI simulations, lab validation, design reviews, and collaboration with cross‑functional teams

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 3+ years of experience in high-speed digital interface design and/or Signal Integrity simulation/validation.

Responsibilities

• Select and qualify high-speed interface components balancing performance, cost, availability, and manufacturability.
• Own schematic capture for high-speed digital subsystems with net topologies and interface pin assignments.
• Own signal integrity analysis for high-speed interfaces from architecture through production including simulation and lab validation.
• Perform channel modeling and simulation using EM tools to verify interconnect performance meets silicon requirements.
• Participate in schematic and layout reviews providing SI/PI feedback to meet performance and cost targets.
• Validate high-speed interfaces in the lab using oscilloscopes, VNAs, and high-fidelity probing techniques.

Skills

High-speed interfaces

Signal Integrity

Education

Bachelor's degree in Electrical Engineering

Master's degree (preferred)

Tools

Orcad

Allegro

Job description

Amazon LEO is seeking a High Speed Digital Design Engineer in Redmond to own high-speed interfaces (DDR, Ethernet, SerDes) for next‑gen terminal products. You will drive component selection, schematic capture, and signal integrity validation across hardware, silicon, and systems teams to deliver robust, cost‑optimized designs for high‑volume manufacturing.

Responsibilities include channel modeling, SI/PI simulations, lab validation, design reviews, and collaboration with cross‑functional teams