High Speed Analog I/O designer

Broadcom; San Jose (CA); Sur place; USD 144 000 - 230 000; Plein temps

Avantages offerts par ce poste

Equity grant

Annual equity awards

Discretionary bonus

Medical benefits

401K matching

ESP P

Résumé du poste

Broadcom in San Jose seeks an experienced Hardware Engineer to design and optimize interface buffer chips for DDR families in FinFET nodes. You will contribute to DDR I/Os, chiplet interfaces, and RX/AFE design.

Responsibilities include circuit architecture exploration, high-speed DDR design, transmitter/receiver circuits, layout considerations, simulations, and reporting. Collaboration across chip teams and validation against performance targets.

Qualifications

• Education: Master's or Ph.D. in Electrical Engineering or related field.
• Experience: 10+ years in analog design with focus on high-speed RX and AFE design.
• Experience with FinFET technologies.
• Expertise in high-speed DDR I/O interface and chiplet I/O design.
• Knowledge of CTLE, DFE, FEE receiver circuits.
• Knowledge of transmitter circuits such as FIR filter, slew rate control, drivers.
• Familiarity with DDR I/O, reliability/area/layout effects.
• Proficiency with Cadence tools and simulation techniques.

Responsabilités

• Collaborate with chip team to understand specs and identify architectures.
• Design, simulate and optimize high-speed DDR circuits and chiplet I/Os.
• Develop transmitter/receiver circuits including CTLE, VGA, DFE; optimize performance, power, and area.
• Explore architectures addressing bottlenecks to improve power, area and performance.
• Oversee physical layout to minimize parasitics and variation impact.
• Perform thorough simulations; troubleshoot and implement fixes.
• Create detailed design reports and analyze silicon data for improvements.
• Stay abreast of industry trends and propose innovative solutions.

Connaissances

High-speed DDR I/O interface

Analog front-end design

Chiplet I/O design

CTLE/DFE/FEE

FinFET technologies

Signal integrity

Power management

Troubleshooting/analysis

Cross-functional collaboration

Formation

Master's or Ph.D. in Electrical Engineering

Outils

Cadence Virtuoso

Maestro

Spectre

HSPICE

Description du poste

USA-California-San Jose-1320 Ridder Park Drive

Full time

R026574

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Job Description:

As a Hardware Engineer, you will play a key role in designing and optimizing cutting-edge interface buffer chips for DDR/LP5/5X/6, chiplets and beyond in the latest FinFET process nodes. Your expertise in DDR I/Os, chip-chip interface I/Os and receiver (RX) design will be pivotal in developing high-performance solutions.

Responsibilities:

• Working with the chip team to understand specifications and identify potential circuit architectures and successful design strategies.

• Design, simulation and optimization of high-speed DDR circuits and chiplet I/Os.

• Design and enhance transmitter and receiver circuits including CTLE, VGA, DFE and slicers focusing on performance metrics such as sensitivity, linearity and power consumption.

• Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets

• Oversee physical layout to minimize the effect of parasitics and process variation.

• Conduct thorough simulations to validate design performance and reliability. Troubleshoot and implement corrective actions as needed.

• Create clear and detailed design reports.

• Analyze customer silicon data for design enhancement.

• Stay current with industry trends and emerging technologies. Suggest and implement innovative solutions to enhance product performance and capabilities.

Qualifications:

• Education: Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.

• Experience: At least 10 years of experience in analog design, with a focus on high-speed RX and Analog-Front-End design.

• Experience with FinFET technologies.

• Expertise in high-speed DDR I/O interface, chip-chip interface design and optimization.

• Strong knowledge of analog receiver circuits such as CTLE, DFE, FEE.

• Sound knowledge of transmitter circuits such as FIR filter, slew rate control, voltage and current mode drivers.

• Knowledge of design for reliability ( EM, IR, aging, self-heating ) and layout effects (matching, reliability, proximity effects etc.)

• Familiarity with custom digital design (i.e. high-speed logic paths, Serializer, De-serializer).

• Proficiency with analog design tools (e.g., Cadence Virtuoso, Maestro, Spectre, HSPICE) and simulation techniques.

• Understanding of signal integrity, timing analysis and power management.

• Problem-Solving: Strong analytical and problem-solving skills, with the ability to resolve complex design challenges

• Communication: Excellent verbal and written communication skills, with the ability to clearly convey technical information to stakeholders.

• Teamwork: Ability to work effectively within a cross-functional team and manage multiple priorities

• Familiarity with industry standards and protocols related to DDR I/O, chiplet I/O and RX design

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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