High Speed Analog I/O designer

Front Door Defense; San Jose (CA); On-site; USD 143,800 - 230,000; Full time

Job summary

Broadcom is seeking a Hardware Engineer in San Jose to lead the design of high-speed analog I/O front-ends for DDR interfaces. You will design, simulate, and optimize DDR circuits, RX and TX I/O, in FinFET nodes, working with cross-functional teams to deliver best-in-class performance.

Requires 10+ years in analog/RX design, DDR I/O expertise, and Cadence tool proficiency. Broadcom offers a competitive package and equity incentives, with a focus on innovation and reliability.

Qualifications

• Master's or Ph.D. in Electrical/Electronics Engineering.
• 10+ years of analog design experience focusing on high-speed RX and AFE.
• Experience with FinFET technologies.
• Expertise in DDR I/O interface and chiplet I/O.
• Familiarity with reliability and layout effects.

Responsibilities

• Collaborate with chip team to define architectures and design strategies.
• Design, simulate, and optimize high-speed DDR circuits and I/O.
• Develop transmitter/receiver circuits (CTLE, VGA, DFE, slicers) for performance targets.
• Lead layout optimization to minimize parasitics and variations.
• Run thorough simulations, troubleshoot, and prepare design reports.
• Analyze silicon data for design improvements.
• Stay current with industry trends and propose innovations.

Skills

Analog design

DDR I/O design

Front-end design

FinFET tech

Transmitter/Receiver circuits

Cadence tools

Signal integrity

Team collaboration

Education

Master's or Ph.D. in Electrical Engineering

Tools

Cadence Virtuoso

Maestro

Spectre

HSPICE

Job description

High Speed Analog I/O designer

Lead design of high-speed analog I/O front-ends for next-gen DDR interfaces

Location: San Jose, California

Compensation: $143,800 - 230,000 USD / year

About The Role

Hardware Engineer

As a Hardware Engineer, you will play a key role in designing and optimizing cutting-edge interface buffer chips for DDR/LP5/5X/6, chiplets and beyond in the latest FinFET process nodes. Your expertise in DDR I/Os, chip-chip interface I/Os and receiver (RX) design will be pivotal in developing high-performance solutions.

Responsibilities:

• Working with the chip team to understand specifications and identify potential circuit architectures and successful design strategies.
• Design, simulation and optimization of high-speed DDR circuits and chiplet I/Os.
• Design and enhance transmitter and receiver circuits including CTLE, VGA, DFE and slicers focusing on performance metrics such as sensitivity, linearity and power consumption.
• Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets
• Oversee physical layout to minimize the effect of parasitics and process variation.
• Conduct thorough simulations to validate design performance and reliability. Troubleshoot and implement corrective actions as needed.
• Create clear and detailed design reports.
• Analyze customer silicon data for design enhancement.
• Stay current with industry trends and emerging technologies. Suggest and implement innovative solutions to enhance product performance and capabilities.

Qualifications:

• Education: Master\'s or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.
• Experience: At least 10 years of experience in analog design, with a focus on high-speed RX and Analog-Front-End design.
• Experience with FinFET technologies.
• Expertise in high-speed DDR I/O interface, chip-chip interface design and optimization.
• Strong knowledge of analog receiver circuits such as CTLE, DFE, FEE.
• Sound knowledge of transmitter circuits such as FIR filter, slew rate control, voltage and current mode drivers.
• Knowledge of design for reliability (EM, IR, aging, self-heating) and layout effects (matching, reliability, proximity effects etc.)
• Familiarity with custom digital design (i.e. high-speed logic paths, Serializer, De-serializer).
• Proficiency with analog design tools (e.g., Cadence Virtuoso, Maestro, Spectre, HSPICE) and simulation techniques.
• Understanding of signal integrity, timing analysis and power management.
• Problem-Solving: Strong analytical and problem-solving skills, with the ability to resolve complex design challenges
• Communication: Excellent verbal and written communication skills, with the ability to clearly convey technical information to stakeholders.
• Teamwork: Ability to work effectively within a cross-functional team and manage multiple priorities
• Familiarity with industry standards and protocols related to DDR I/O, chiplet I/O and RX design

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00. As a valued member of our team, you\'ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company\'s growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.