Head of Test Development Engineering

Ethernovia; San Jose (CA); On-site; USD 220,000 - 280,000; Full time

Benefits offered by this job

Pre-IPO stock options

Flexible hours

Medical, dental and vision insurance

Job summary

Ethernovia, Inc. seeks a Head of Test Development Engineering to lead transition from NPI to high-volume manufacturing for automotive-grade networking chips. You will own end-to-end test architecture, infrastructure, and methodology, bridging world-class designs with wafer and system testing.

Based in San Jose, CA, you will guide labs and cross-functional teams to deliver scalable test solutions, DRIVE DFT/DFM/DFD requirements, and ensure robust testing for Ethernet PHY devices.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical field.

Responsibilities

• End-to-end test architecture, infrastructure, hardware and methodology ownership from pre-silicon to post-silicon, coordinating with Arch, Design, DFT, Security, SW/FW, System, Product and Q&R.
• Own early engagement with Arch/DFT, System/SW and Security on ATE/SLT architecture and DFM/DFD to ensure debugability and testability to spec.
• Deliver manufacturing test programs from NPI bring-up to high volume manufacturing for high-speed Ethernet switch and PHY products.
• Own design of test boards ensuring SI/PI and test implementation across wafer, final test and system level test.
• Manage test labs, OSAT, engagement with tester vendors, prober, probe cards, load boards, system boards, sockets, handlers and change kits.

Job description

About Ethernovia, Inc.

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications. Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date: Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital) Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025. March 2026: Ethernovia Announces HSB-Enabled Networking Board for NVIDIA Holoscan Platforms January 2024: Our CEO Ramin Shirani Named MotorTrend Software-Defined Vehicle Innovator Awards Winner (ethernovia.com) September 2023: Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news With talented employees on 4 continents, we have filed 50+ patents to date. Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Head of Test Development Engineering Summary

The Head of Product Development Engineering will be responsible for taking Ethernovia’s products from NPI to HVM. This position requires a leader who is hands‑on with semiconductor test development. You will bridge the gap between world‑class networking chip designs and high‑volume, automotive‑grade silicon testing. The position is based in San Jose, CA.

Key Responsibilities

• End to end, test architecture, infrastructure, hardware and methodology ownership from pre-silicon to post-silicon , working with Arch, Design, Desing verification, DFT, Security, SW/FW, System, Product and Q&R.
• Own early engagement with Arch/DFT, System/SW and Security, on ATE and SLT test architecture and DFM / DFD to ensure debug ability and testability to spec.
• Deliver manufacturing test programs from NPI bring-up to high volume manufacturing for high-speed Ethernet switch and PHY products ensuring signal integrity and power/performance standards are maintained at scale.
• Own design of test boards ensuring SI/PI and test implementation across wafer test, final test and system level test, ensuring robustness and meeting test time.
• Manage test labs, OSAT (test house), engagement with vendors for tester, prober, probe card, load board, system board, socket, handler, change kit and TCU.

Required Experience & Skills

• Professional Background Bachelor's or Master's degree in Electrical Engineering or a related technical field.
• 12+ years of experience in fabless semiconductor operations, specifically for complex, high-performance SOCs or networking ICs.
• Expert in ATE 93K platform and Smartest, test method libraries and design of test hardware with robust SI/PI for wafer and final test.
• Expertise with iJTAG, Scan (SSN), MBIST, Sensor, SerDes, LSIO/HSIO testing, security fusing and test automation for multi-site (x8, x16) parallel testing.
• Expert in SLT testing using bare-metal, functional DVFS and benchmark testing and expert in multi-site handler automation framework and test log standards.
• Experience with Analog characterizing high-speed communication chips on ATE and System to ensure all IO parameters are characterized and tested.
• Experience defining DFT/DFM/DFD requirements for Ethernet PHY and Switch products and experience with scan and memory dump for debug.
• Experience navigating the Automotive electronics ecosystem, including IATF 16949, ISO 26262, Safe launch and PPAP (Production Part Approval Process).

Technical Leadership & Skills

• Understanding of high-bandwidth data-path products (Ethernet, Switching, or high-speed SerDes).
• Expert level experience with ATE and SLT test hardware, test program development, high speed IO analog characterization and test automation.
• Understanding of product life cycle from concept to end of life and leading pre‑silicon review and readiness to enable seamless post‑silicon bring‑up.

Nice to Have (The "Competitive Advantage")

• Experience with simulation, pattern generation, and pattern conversion.
• Experience delivering high speed SerDes products to Tier-1 automotive OEMs.
• Experience negotiating with and managing hardware vendors and OSATs.

What You Can Expect From Ethernovia

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary

Benefits

• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range

The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $220,000 - $280,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

Principals Only (No Agencies) #LI-Hybrid