Head of Memory Architecture (Xora Portfolio Company)

Xora Innovation; San Jose (CA); On-site; USD 250,000 - 380,000; Full time

Job summary

Xora Innovation, a Silicon Valley stealth startup in San Jose, seeks a Head of Memory Architecture to lead the design of a purpose-built memory for AI inference computing and data center workloads. You will drive architectural strategy, model memory subsystems, and optimize performance, power, and cost in collaboration with device technology and commercial teams.

The role demands a strong track record in memory architecture, a PhD/MS and 10+ years in the field, and the leadership skills to align

Qualifications

• MS or PhD in CS/CE/EE preferred.
• 10+ years in memory architecture, ideally with leading memory IDMs.
• Deep understanding of memory issues in AI inference computing.

Responsibilities

• Architect memory subsystems for AI inference computing.
• Model, analyze trade-offs among footprint, bandwidth, latency, power, and cost.
• Collaborate with SOC architects, NPI teams, and silicon design to accelerate product readiness.

Job description

ABOUT THE COMPANY

We are a Silicon Valley, San Jose based stealth start-up and are looking for a passionate, ambitious individual who shares our vision of next generation disruptive memory solutions for Agentic AI inference and high performance data center computing applications.

This is an impactful and senior leadership role allowing you to mastermind the realization of our strategic ambitions and shape the direction of our product portfolio development.

ABOUT THE ROLE

In your role as Head of Memory Architecture, you will lead the architectural design of our disruptive product which is a purpose-built memory for AI inference computing, building on your extensive knowledge and industry experience combined with our proprietary in-house device technology capabilities. It is a senior engineering role responsible for designing, modeling, and optimizing the memory subsystems for a new memory category and product for AI inference computing. Close collaboration with device technology and commercial development teams is an essential element of this role.

CORE RESPONSIBILITIES

• Architecture & Trade-off Analysis: Balance memory footprint, bandwidth, latency, power efficiency, density, silicon area, and cost/bit.
• Subsystem Design: Design memory vaults and hierarchies, on-chip interconnects, sense amplifiers and address translation with emphasis on high granularity and bandwidth
• Workload Optimization: Analyze state-of-the-art Agentic AI inference applications, software, AI inference models, leading edge SOCs for data center workloads and how they interact with memory to reduce bottlenecks. Benchmark leading edge AI inference SOC architectures and workload management specifics vis a vis competing memory architectures and devices including our disruptive memory solution.
• Novel Bit Cell and Device Architectures: Ability to understand and leverage our core materials and device technology to realize a category defining memory for inference computing
• Cross-Functional Collaboration: Partner with SOC architects, NPI teams, silicon design and technology teams to drive acceleration of the product to market.

REQUIRED QUALIFICATIONS & SKILLS

• Education: M.S. or Ph.D. in Computer Science (CS), Computer Engineering (CE), or Electrical Engineering (EE) preferred.
• Experience: 10+ years in memory architecture, preferably the leading memory IDMs.
• Technical Knowledge:
  • Deep grasp of state-of-the-art memory issues and challenges particularly associated with Agentic AI inference computing.
  • Power, performance, area and cost (PPAC) analysis and modeling.
• Network Connections: Broad network of relevant industry and academia experts to deepen our understanding and to evangelize our memory offering.