Hardware Systems Architect

United States Digital Space LLC; San Francisco (CA); On-site; USD 320,000 - 485,000; Full time

Job summary

United States Digital Space LLC is seeking a senior hardware systems architect to lead system-level design for high‑scale AI compute platforms. You will own architecture across power, cooling, interconnect, and data/control planes, partner with ML performance and datacenter teams, and drive validation strategies.

You’ll write specs, review partner designs, and shape hardware roadmaps with a focus on reliability, scalability, and AI-assisted engineering.

Qualifications

• Bachelor’s degree in a technical field or equivalent experience.
• 8+ years in hardware-systems architecture or engineering for large-scale compute.
• Experience owning architecture through bring-up and production deployment.
• Proven track record reviewing external hardware designs to a spec.

Responsibilities

• Own system path-finding and architecture across compute deployments.
• Write and own high-level requirements and specs—system, board, interface, rack.
• Review partner and vendor designs against requirements and surface risks.
• Drive interconnect and networking architecture for scale-out fabrics.
• Lead board-, chassis-, and system-level architecture with partners.
• Develop performance simulations and hardware models for evaluation.
• Define validation and qualification strategy for new platforms.
• Collaborate with ML performance and infra software teams on hardware decisions.

Skills

Hardware-systems architecture

Power & thermal design

Interconnect design

System validation & testing

Vendor collaboration

Technical leadership

Autonomy in fast environment

Written communication

Education

Bachelor’s degree in EE/CE/ME/CS

Tools

PCIe/CXL expertise

BMC firmware

Telemetry tooling

3D CAD tools

Job description

About the company

the company’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems.

About the role

the company trains and serves frontier AI models on some of the largest and most diverse accelerator fleets in the world, and the hardware those models run on is one of the most direct levers we have on capability, cost, and reliability. Our Hardware Systems team owns the system-level architecture of that compute — from the package boundary out through boards, racks, interconnect, power, cooling, and the datacenter interface.

We're hiring senior hardware systems architects and technical leads who can work broadly across the hardware stack and go deep where it's needed, and who have the judgment to make and own directional calls — what to build, what to buy, what to co‑design with a partner. You'll set architecture, write the specs that partners and internal teams build against, and own the validation and qualification strategy that proves the result.

The skillsets we need span power, cooling, mechanical, interconnect, signal integrity, data and control plane, system management, reliability and serviceability — applied across networking, compute, storage, and accelerator systems.

You'll work closely with our ML performance, infrastructure software, supply chain, and datacenter teams, and directly with hardware vendors and partners across the stack. And because this is the company, you'll have Claude as a genuine collaborator — we expect this team to push on what AI‑assisted hardware design and review can look like.

Key responsibilities

• Own system path-finding and architecture for your domain across the breadth of compute the company deploys — from concept and requirements through spec, design review, and deployment — and act as a reviewer and thought partner across the others.
• Write and own high-level requirements and specifications — system, board, interface, rack — that partners and internal teams build against.
• Review partner and vendor designs against our requirements, make the build / buy / co-design calls with supply chain and partnership teams, and surface misalignment or schedule risk early enough to act on it.
• Drive the interconnect and networking architecture that ties our systems together — scale-up and scale-out fabrics, NICs and switches, optics, and topology.
• Drive board-, chassis-, and system-level architecture with our partners — major component placement, PCB architecture, connector and cable design, and power and thermal budgeting — at the chassis, rack, and data‑hall level.
• Develop performance simulations, hardware models, and "what‑if" scenarios to evaluate and choose between candidate hardware architectures.
• Define validation, bring‑up, and qualification strategy for new platforms — including the telemetry and reliability targets they need to hit in the fleet — and track the technology roadmaps and vendor landscape that shape what we deploy in the short and long term.
• Partner with ML performance and infrastructure software teams so hardware decisions land well for the workloads that actually run on them.
• Help shape how hardware engineering operates at the company — develop and apply AI‑assisted approaches to design, spec review, and validation; establish review forums, spec standards, and partner engagement.

Minimum qualifications

• Deep, hands‑on expertise in at least one core hardware‑systems domain (e.g., interconnect, power, thermal) for large‑scale compute or networking systems.
• Experience owning hardware system architecture at scale — machine, rack, row, and cluster — and authoring specifications and requirements.
• Experience taking hardware from architecture through bring‑up and high‑volume production deployment.
• Experience working with external hardware vendors and partners — reviewing their designs and holding them to a specification.
• Ability to reason about trade‑offs across adjacent hardware domains (e.g., interconnect power thermal mechanical) rather than within a single one.
• Track record of technical leadership — owning directional decisions and their consequences, and driving alignment across teams and partners.
• Comfort operating with high autonomy and limited process in a fast‑moving, ambiguous environment.
• Strong written communication — you'll write specs and reviews that many teams depend on.

Preferred qualifications

• 8+ years in hardware systems architecture or engineering for hyperscale, HPC, AI/ML, or high‑end networking platforms.
• Experience with AI accelerator systems (GPU, TPU, or other custom ASIC platforms) and their scale‑up / scale‑out fabrics.
• Familiarity with the chip-package-system interface and co‑design.
• Experience establishing a new function, program, or engineering practice.
• Comfort working with — and curiosity about pushing — AI tools as part of an engineering workflow.
• Degree in EE, CE, ME, CS, or a related field, or equivalent experience.
• Depth in one or more of:
  • High‑speed SerDes, PCIe/CXL, Ethernet/InfiniBand, and optical interconnect.
  • BMC and platform firmware, hardware root of trust, and secure boot.
  • 48V/HVDC power delivery and direct liquid cooling.
  • Fleet‑scale reliability engineering and RAS architecture.
  • Signal and power integrity.

Representative projects

• Define the scale‑up and scale‑out interconnect architecture for a next‑generation training platform, from link budget and topology through switch / NIC / optics selection and the bring‑up and validation plan.
• Architect the management and control plane for a new hardware system: BMC and host control, power / reset sequencing, secure boot and attestation, and the telemetry surface the fleet needs.
• Own the rack‑level power and thermal architecture for a liquid‑cooled accelerator rack, and the interface spec between that rack and the datacenter that hosts it.
• Build the reliability model and RAS strategy for a multi‑thousand‑node fleet — failure budgets, derating policy, telemetry requirements, and serviceability targets — and drive the design changes that hit them.
• Run the technical evaluation of a partner's proposed system design against our requirements, write up where it falls short, and drive the changes end to end.
• Prototype an AI‑assisted workflow for partner design review and spec consistency checking, and put it to work on a live platform.

The annual compensation range for this role is listed below.

For sales roles, the range provided is the role’s On Target Earnings ("OTE") range, meaning that the range includes both the sales commissions/sales bonuses target and annual base salary for the role.

Annual Salary: $320,000 — $485,000 USD

Logistics

Minimum education: Bachelor’s degree or an equivalent combination of education, training, and/or experience

Required field of study: A field relevant to the role as demonstrated through coursework, training, or professional experience

Minimum years of experience: Years of exp