Hardware Engineer Sr Staff, Signal Integrity

Juniper Networks; Sunnyvale (CA); On-site; USD 194,000 - 280,000; Full time

Job summary

An established industry player is seeking a talented engineer to join their collaborative Signal Integrity team. This role focuses on system-level design and cutting-edge technologies, analyzing and optimizing high-speed interconnects for robust performance. You will work closely with cross-functional teams to perform channel margin analysis and develop simulation models, ensuring that the designs meet rigorous standards. With a strong emphasis on teamwork and innovation, this position offers a unique opportunity to contribute to advanced solutions in a dynamic environment. If you have a passion for technology and a wealth of experience, this is the perfect opportunity for you.

Benefits

Medical Benefits

401(k) Eligibility

Vacation

Sick Time

Parental Leave

Qualifications

• 15+ years of experience in Signal Integrity design and analysis.
• Proficient with lab equipment and high-speed SerDes technologies.

Responsibilities

• Collaborate on SI design and analysis of interconnects.
• Develop and validate SerDes channel simulation models.

Skills

Signal Integrity Design

High-Speed Interconnects

Channel Margin Analysis

Debugging Skills

Presentation Skills

Education

Bachelor's Degree

Master's Degree

PhD

Tools

Ansys HFSS

ADS

SPICE

MATLAB

Cadence Allegro

Job description

Join a collaborative, centralized Signal Integrity (SI) team focused on system-level SI design and cutting-edge technologies. You will analyze, design, and optimize high-speed interconnects, enabling robust performance across a wide range of system architectures.

Key Responsibilities:

• Collaborate on SI design and analysis of interconnects including chip-to-chip, board-to-board, backplane, and chassis-level solutions.
• Perform channel margin analysis to evaluate trade-offs between package, PCB, and connector design.
• Develop and validate SerDes channel simulation models; correlate simulation results with test structures and measurement data.
• Collaborate with SerDes vendors to fine-tune Tx/Rx models and optimize signal quality (TP1A, BER).
• Conduct PCB timing analysis; implement SI rules in collaboration with board and layout engineers.
• Develop and document layout/SI checklists and design guidelines.
• Execute SI design validation tests (DVT) and correlate lab measurements with simulations.
• Provide technical assessments and updates to the SI management team.

Minimum Qualifications:

• Proficiency with lab equipment: oscilloscopes, VNAs, TDRs, spectrum analyzers, phase noise analyzers.
• Strong debugging skills and hands-on lab experience.
• Effective team player comfortable working in a matrixed, cross-geographic environment.
• Ability to leverage existing SI designs and contribute to shared team knowledge.
• Strong presentation skills; capable of communicating technical concepts in team forums.
• Proficient with design and simulation tools: Ansys HFSS, ADS, SPICE, MATLAB, Cadence Allegro.
• Educational Requirements:
  • BS with 15+ years experience
  • MS with 13+ years
  • PhD with 11+ years
• Experience with high-speed SerDes technologies (100G, 56G PAM4, 25G NRZ) is a plus.

Minimum Salary: $194,400.00

Maximum Salary:$279,450.00

The pay range for this position is expected to be between $194,400.00 and $279,450.00/year; however, the base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position also includes medical benefits, 401(k) eligibility, vacation, sick time, and parental leave. Additional details of participation in these benefit plans will be provided if an employee receives an offer of employment.

If hired, employee will be in an “at-will position” and the Company reserves the right to modify base salary (as well as any other payment or compensation program) at any time, including for reasons related to individual performance, Company or individual department/team performance, and market factors.

Juniper’s pay range data is provided in accordance with local state pay transparency regulations. Juniper may post different minimum wage ranges for permanent residency petitions pursuant to US Department of Labor requirements.