Hardware Emulation Engineer

Intelliswift - An LTTS Company; Sunnyvale (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Intelliswift - An LTTS Company in Sunnyvale, CA is seeking a simulation acceleration specialist to maintain and optimize emulation environments, port SystemVerilog/UVM testbenches, and accelerate project milestones.

You will collaborate with RTL, DV, firmware, and software teams, integrating VIPs and debugging RTL on Palladium/ZeBu platforms to meet aggressive delivery timelines.

Qualifications

• Experience maintaining simulation acceleration environments using Palladium and ZeBu.
• Ability to port SystemVerilog/UVM testbenches to acceleration platforms.
• Experience partitioning verification environments for performance.
• Experience debugging RTL and testbenches on emulation platforms.

Responsibilities

• Maintain simulation acceleration and emulation environments using Cadence Palladium and/or Synopsys ZeBu.
• Port existing SystemVerilog/UVM testbenches to acceleration/emulation platforms.
• Partition verification environments between host and emulator while maintaining functional correctness and performance.
• Optimize verification environments to reduce compile time and improve simulation performance.
• Enable long-running regression tests and software-driven validation on acceleration platforms.
• Integrate third-party VIPs and develop custom transactors where required.
• Debug RTL, testbench, and acceleration-specific issues using waveform and emulator debug tools.
• Collaborate with RTL designers, DV engineers, architects, firmware, and software teams to accelerate project milestones.

Skills

Cadence Palladium

Synopsys ZeBu

SystemVerilog/UVM

Emulation Platforms

Tools

Cadence Palladium

Synopsys ZeBu

RTL Debug Tools

Waveform Debug Tools

Job description

Employment Type: Full-Time with L&T Technology Services (LTTS).

We are looking for a simulation acceleration candidate with the following qualifications:

Maintain simulation acceleration and emulation environments using Cadence Palladium and/or Synopsys ZeBu.

Port existing SystemVerilog/UVM testbenches to acceleration/emulation platforms.

Partition verification environments between host and emulator while maintaining functional correctness and performance.

Optimize verification environments to reduce compile time and improve simulation performance.

Enable long-running regression tests and software-driven validation on acceleration platforms.

Integrate third-party VIPs and develop custom transactors where required.

Debug RTL, testbench, and acceleration-specific issues using waveform and emulator debug tools.

Collaborate with RTL designers, DV engineers, architects, firmware, and software teams to accelerate project milestones.