Hardware Architect - Cognitive Robotics (human)

NEURA Robotics; Germany (OH); On-site; USD 140,000 - 180,000; Full time

Job summary

NEURA Robotics seeks a Senior Hardware Architect to define the hardware blueprint for its cognitive robots. You will own the overall hardware system architecture, translate product requirements into constraints, and ensure all subsystems fit into a scalable, manufacturable solution.

You will lead architecture governance, drive component selection for performance and cost, and collaborate with AI/software teams to meet real-time control and inference needs.

Qualifications

• Master's degree in Electrical/Computer Engineering, Mechatronics or related field.
• 8+ years hardware development experience in embedded or cyber-physical systems.
• Production-ready hardware architecture experience (EVT/DVT to production).
• Experience with embedded compute platforms (ARM, NVIDIA Jetson, FPGA).
• Power system architecture and EMC at system level.
• Knowledge of high-speed data/communication backbones (EtherCAT, CAN-FD, TSN).
• DFM/DFT experience for high-volume manufacturing.
• Strong cross-functional communication with product, AI/Software, and hardware teams.
• Robotics/automotive/aerospace/industrial hardware experience preferred.
• Fluent English; German is a practical advantage.

Responsibilities

• Own hardware system architecture for the robot platform and ensure scalability.
• Translate product requirements into hardware constraints across electronics and mechanicals.
• Lead hardware architecture reviews and enforce design standards.
• Evaluate and select key platform components balancing performance and cost.
• Interface hardware with software/AI teams to expose required capabilities.
• Drive DFM/DFT and design-for-cost from day one for mass production.
• Provide mentorship to engineers and support team growth in hardware.

Skills

Fluent English

German language advantage

Education

Master's degree in Electrical/Computer Engineering or Mechatronics

PhD is a plus

Tools

ARM Cortex-A/M

NVIDIA Jetson

FPGA/eFPGA

Power management ICs

EtherCAT/CAN-FD/TSN

EMC considerations

Job description

This is where Artificial Intelligence comes to life. The Hardware Department designs, constructs, and optimizes all physical components of our cognitive robots. As NEURA scales from prototype to production of five million robots, the decisions made at the architecture level today will shape the platform for years to come. The Hardware Architect is the person who makes those decisions — with the authority to define the blueprint and the accountability to make it work in the real world.

Your mission & challenges

You define the hardware blueprint for the world's most advanced cognitive robots.

NEURA's humanoid robot is a deeply complex cyber-physical system: distributed computing, high-density power electronics, a body-area sensor network, real-time actuation control, and a cognitive AI stack — all packed into a human-scale form factor and designed for mass production. The Hardware Architect owns the overall hardware system architecture, translates product requirements into physical design constraints, and ensures that every sub-system — from PCBAs to cabling to compute modules — fits coherently into a scalable, manufacturable whole.

• Hardware system architecture: Define and maintain the top-level hardware architecture of the robot platform — compute topology (SoCs, MCUs, edge AI accelerators), power architecture (bus voltages, distribution, protection), communication backbone (EtherCAT, CAN-FD, Ethernet, SerDes), and sensing architecture (sensor selection, placement, interface strategy).
• Requirements & partitioning: Translate product, performance, and safety requirements into hardware requirements; partition functionality across electronics, embedded software, and mechanical subsystems; manage technical interfaces between all hardware disciplines.
• Architecture governance: Lead hardware architecture reviews; define and enforce hardware design standards, interface control documents, and design rules across the electronics, firmware, and mechanical teams.
• Technology selection: Evaluate and select key platform components — compute SoCs, power management ICs, communication controllers, sensor ICs — balancing performance, availability, NRE cost, and long-term scalability.
• Cross-disciplinary integration: Serve as the primary technical interface between the hardware team and software/AI architecture teams; ensure the hardware platform exposes the right capabilities (memory bandwidth, I/O, compute) to meet AI inference and real-time control requirements.
• DFM and scalability: Ensure architectural decisions are compatible with high-volume manufacturing; drive design-for-reliability, design-for-testability (DFT), and design-for-cost principles from day one.
• Technical mentorship: Provide technical guidance and mentorship to senior electronics, firmware, and system engineers; support hiring and team growth in the hardware domain.

What we can look forward to

A rare combination: system-level thinker and hands-on hardware expert.

You are a senior hardware engineer or architect who has seen the full lifecycle of a complex embedded hardware product — from architecture concept through mass production — and who understands what it takes to get architecture right at each stage. You lead by technical authority, not organizational position, and you thrive in environments where the architecture is still being shaped.

• Master's degree in Electrical Engineering, Computer Engineering, Mechatronics, or a closely related field; PhD is a plus but not required.
• 8+ years of professional experience in hardware development for complex embedded or cyber-physical systems, with at least 3 years in a hardware architecture, lead engineer, or staff engineer role.
• Proven track record of defining and delivering multi-disciplinary hardware system architectures — from concept through EVT/DVT and into production — for products combining high-speed compute, power electronics, and real-time sensing.
• Deep understanding of embedded compute platforms (ARM Cortex-A/M, NVIDIA Jetson class, FPGA/eFPGA) and the trade-offs between centralized and distributed compute topologies.
• Strong command of power system architecture: multi-rail SMPS design, battery/BMS integration, load analysis, power sequencing, and EMC mitigation at the system level.
• Experience defining communication backbone architectures for real-time distributed systems (EtherCAT, CAN-FD, TSN Ethernet, SpaceWire, or similar).
• Familiarity with functional safety standards and the ability to translate safety requirements into hardware architecture constraints (redundancy, monitoring, safe states).
• Experience with DFM/DFT in high-volume hardware — able to drive architecture choices that remain manufacturable and testable at scale.
• Strong cross-functional communication skills: able to represent hardware architecture in discussions with product management, AI/software architects, supply chain, and executive leadership.
• Experience in robotics, automotive (ADAS/body electronics), aerospace, or industrial automation hardware is strongly preferred.
• Fluent English; German is a practical advantage.