GPU PCIe & Boot Architect — Designing Next-Gen Interconnects

NVIDIA; Santa Clara (CA); On-site; USD 108,000 - 196,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara, CA is seeking a GPU PCIe and Boot Architect to design the architecture and infrastructure for boot, PCIe/CXL enumeration, and capability discovery. You will collaborate with software, hardware, and verification teams globally to implement the next generation of GPUs.

You’ll create functional and performance models in C++, develop test plans, and support post-silicon validation. This role requires strong CS/EE background and hands-on HW/SW experience.

Qualifications

• Pursuing or recently completed a BS or MS in Computer Architecture, Computer Science, or Electrical Engineering (or related degree) or equivalent experience.
• Coursework in Computer Architecture, Operating systems, and/or system architecture.
• Experience with HW/SW interactions.
• Experience building software models, diagnostic tests, and/or directed function and performance tests.
• Strong proficiency in C++ (previous project or internship experience is preferred)

Responsibilities

• Understand how the GPU sub-system modules interoperate and interact with the overall system.
• Architect and plan features in concert with software, hardware, and verification teams across the globe to implement the next iteration of GPUs.
• Create functional and performance models, often in C++, along with test plans to validate the features you design.
• Actively support post-silicon validation activities.

Skills

C++ proficiency

HW/SW co-design

Software modeling

System architecture coursework

Education

BS or MS in Computer Architecture/CS/EE

Job description

NVIDIA in Santa Clara, CA is seeking a GPU PCIe and Boot Architect to design the architecture and infrastructure for boot, PCIe/CXL enumeration, and capability discovery. You will collaborate with software, hardware, and verification teams globally to implement the next generation of GPUs.

You’ll create functional and performance models in C++, develop test plans, and support post-silicon validation. This role requires strong CS/EE background and hands-on HW/SW experience.