GPU Kernel Engineer-High-Performance AI Primitives (Hybrid)

Talanto

Hillsboro, Northern (OR, KY)

Hybrid

USD 195,000 - 276,000

Full time

13 hours ago
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Benefits offered by this job

Hybrid work model
Stock bonuses
Health insurance
Retirement plan
Paid vacation

Job summary

Talanto is seeking a Senior GPU Performance Software Engineer to contribute to oneDNN development and low-level optimization for AI workloads on GPUs. This is a low-level role focusing on high-performance math primitives, kernel design, and codegen for next-generation accelerators.

You will collaborate with hardware teams and open-source communities, optimize FP16/BF16 paths, and shape performance across OpenCL/CUDA/HIP stacks while supporting CI and validation pipelines.

Qualifications

  • Education: BSc, MSc, or PhD in Computer Science, Computer Engineering, Mathematics, Physics, or related fields.
  • 5+ years of professional software development with expert-level C++.
  • 2+ years of GPU kernel optimization or 5+ years low-level optimization on CPUs.
  • Strong foundations in computer architecture, memory subsystems and parallel programming.

Responsibilities

  • Develop high-performance GEMM, convolution, and attention kernels for AI workloads.
  • Design scalable JIT and codegen infrastructure for GPU kernel generation.
  • Implement fusion and memory-traffic optimizations to maximize hardware utilization.
  • Profile and optimize mixed-precision and quantized execution paths (BF16, FP16, INT8, FP8, FP4).

Skills

Modern C++
GPU kernel optimization
Parallel programming
Performance tuning

Education

BSc/MSc/PhD in CS or related

Tools

SYCL/DPC++
OpenCL/CUDA/HIP

Job description

Talanto is seeking a Senior GPU Performance Software Engineer to contribute to oneDNN development and low-level optimization for AI workloads on GPUs. This is a low-level role focusing on high-performance math primitives, kernel design, and codegen for next-generation accelerators.

You will collaborate with hardware teams and open-source communities, optimize FP16/BF16 paths, and shape performance across OpenCL/CUDA/HIP stacks while supporting CI and validation pipelines.

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