GPU Kernel Engineer for Distributed ML & Inference

Advanced Micro Devices; Bellevue, Northern (WA, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Advanced Micro Devices (AMD) is seeking a PMTS Software Development Engineer to develop and optimize low-level GPU kernels for accelerating ML inference and training. You will maximize efficiency, reduce execution time, and ensure accuracy while enabling distributed model training across multiple GPUs and nodes.

The role involves profiling, parallel computing techniques, multi-threading, and synchronization to enhance scalability.

Qualifications

• Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Software Engineering, or related field.
• Alternate: Bachelor’s degree with 7 years of progressive experience in the job offered or closely related engineering role.
• Position requires two years of experience in hardware design, microarchitecture, Verilog RTL coding, and FPGA.
• Strong collaboration with arch and software teams to define microarchitecture specifications.

Responsibilities

• Develop and optimize low-level GPU kernels to accelerate ML model inference and training.
• Maximize computational efficiency and reduce execution time while preserving model accuracy.
• Design and implement distributed training and inference across multiple GPUs and nodes.

Skills

Hardware design

Verilog RTL

UVM testbench

VLSI design

Scripting (Perl/Python/TCL)

FPGA

Power design concepts

Education

Master’s degree in CS/CE/EE or related field

Bachelor’s degree + 7 years of experience

Tools

Verilog

UVM tooling

FPGA tooling

Job description

Advanced Micro Devices (AMD) is seeking a PMTS Software Development Engineer to develop and optimize low-level GPU kernels for accelerating ML inference and training. You will maximize efficiency, reduce execution time, and ensure accuracy while enabling distributed model training across multiple GPUs and nodes.

The role involves profiling, parallel computing techniques, multi-threading, and synchronization to enhance scalability.