Base Pay Range
$80.00/hr - $90.00/hr
This role is for a senior Front-End (FE) Infrastructure / Verification Engineer responsible for designing, maintaining, and improving complex verification flows and regression systems for large-scale hardware projects.
Key Responsibilities
- Design, support, and continuously enhance scalable and robust FE verification flows
- Own regression management and triage, including debugging coverage issues, regression failures, and flow instability
- Act as the primary technical interface with EDA vendors, especially Synopsys (VCS), handling advanced tool debugging, escalations, and new feature adoption
- Deploy and support RTL architecture tools integrated into FE verification flows
- Maintain and streamline version control workflows using Git, Perforce, and Git-P4
Required Expertise
- 10+ years of experience in FE design verification infrastructure
- Deep hands‑on experience with flow-based regression systems
- Strong knowledge of Synopsys VCS, IES, and xprop configuration
- Proven ability to debug complex verification, coverage, and tool issues
- Advanced experience with Git and Perforce
- Strong communication skills and ability to work independently with vendors and internal teams
Overall:
This is a highly technical, senior-level infrastructure role focused on verification flow ownership, regression stability, and EDA tool expertise, rather than pure RTL or testbench development.
Seniority level: Mid-Senior level
Employment type: Contract
Job function: Engineering and Design
Industry: Semiconductor Manufacturing