FPGA Firmware Lead for Space Mission Systems

Jobtome; Town of Chili (NY); On-site; USD 111,000 - 206,000; Full time

Job summary

L3Harris Technologies is seeking an FPGA Design Engineer – Firmware Lead in Rochester, NY. You will lead FPGA firmware efforts for space mission systems, translating system requirements into FPGA architectures and HDL implementations.

Responsibilities include leading small engineering teams, guiding FPGA development across PCIe, SRIO and SpaceWire interfaces, and ensuring rigorous verification, timing, and integration with circuit cards within a defense/space context.

Qualifications

• Bachelor’s Degree and minimum 9 years of prior relevant experience. Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience.
• Ability to obtain Federal Secret security clearance

Responsibilities

• Lead FPGA Firmware Engineering activities in the Space Mission Systems segment.
• Decompose system requirements to FPGA requirements and specifications.
• Architect FPGA solutions across various technologies or platforms.
• Lead small teams of engineers in FPGA development.
• Develop HDL code for module and top-level, plus testbenches and verification environments.
• Synthesize designs and perform place-and-route timing analysis.
• Verify FPGA simulations and integrate on the circuit card assembly.

Skills

VHDL

FPGA design

PCIe

SRIO

Ethernet

I2C/SPI/RS-232/422

SpaceWire

Xilinx tools

Git/version control

Timing analysis

Education

Bachelor’s degree in engineering or related field

Graduate degree (optional)

13 years equivalent experience in lieu of degree

Tools

Xilinx tool suite

Intel/ Quartus (Place & Route)

Microchip/FPGA toolchains

Job description

L3Harris Technologies is seeking an FPGA Design Engineer – Firmware Lead in Rochester, NY. You will lead FPGA firmware efforts for space mission systems, translating system requirements into FPGA architectures and HDL implementations.

Responsibilities include leading small engineering teams, guiding FPGA development across PCIe, SRIO and SpaceWire interfaces, and ensuring rigorous verification, timing, and integration with circuit cards within a defense/space context.