Fpga Engineer

Actalent; California (MO); On-site; USD 110,000 - 152,000; Full time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Short and long-term disability

Health Spending Account (HSA)

Transportation benefits

Employee Assistance Program

Time Off/Leave

Job summary

Actalent seeks an experienced FPGA Engineer to lead architecture, development and verification of FPGA-based subsystems in Irvine, CA. You will own the design from concept through qualification, verification, integration and manufacturing.

Responsibilities include defining FPGA architecture, RTL development in SystemVerilog or VHDL, and working with Vivado/Xilinx tools. This is a contract onsite role with competitive hourly pay.

Qualifications

• Extensive experience with FPGA, Verilog, VHDL, SystemVerilog.
• Proficiency in using Vivado and Xilinx tools.
• Strong background in digital design and DSP.
• 10+ years of FPGA RTL architecture, development, and verification.

Responsibilities

• Lead the architecture, development, and verification of FPGA-based subsystems.
• Own the design process from concept through qualification, verification, integration, and manufacturing.
• Define FPGA architecture and requirements.
• Develop RTL in SystemVerilog or VHDL.

Skills

FPGA RTL

Verilog

SystemVerilog

VHDL

Vivado

Xilinx tools

Digital design

DSP

10+ years

Tools

Vivado

Xilinx tools

Job description

Job Description

Job Description

Job Title: FPGA Engineer

Job Description

The FPGA Engineer will lead the architecture, development, and verification of FPGA-based subsystems. You will own the design from concept through qualification, verification, integration, and manufacturing. Additional responsibilities include defining FPGA architecture and requirements and developing RTL in SystemVerilog or VHDL.

Responsibilities

• Lead the architecture, development, and verification of FPGA-based subsystems.
• Own the design process from concept through qualification, verification, integration, and manufacturing.
• Define FPGA architecture and requirements.
• Develop RTL in SystemVerilog or VHDL.

Essential Skills

• Extensive experience with FPGA, Verilog, VHDL, SystemVerilog.
• Proficiency in using Vivado and Xilinx tools.
• Strong background in digital design and DSP.
• 10+ years of FPGA RTL architecture, development, and verification.

Job Type & Location

This is a Contract position based out of Irvine, CA.

Pay and Benefits

The pay range for this position is $80.00 - $110.00/hr.

• Medical, dental & vision
• Critical Illness, Accident, and Hospital
• 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
• Life Insurance (Voluntary Life & AD&D for the employee and dependents)
• Short and long-term disability
• Health Spending Account (HSA)
• Transportation benefits
• Employee Assistance Program
• Time Off/Leave (PTO, Vacation or Sick Leave)

Workplace Type

This is a fully onsite position in Irvine,CA.

Application Deadline

This position is anticipated to close on Aug 21, 2026.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [e-mail] for other accommodation options.

San Francisco Fair Chance Ordinance:

Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector:

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI):

We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.