FPGA Design Engineers***MUST have a U.S. Citizenship for the DoD***

Entegee; Cherry Hill Township (NJ); On-site; USD 100,000 - 140,000; Full time

Job summary

Entegee is seeking on-site FPGA Design Engineers for Cherry Hill, NJ or Owego, NY. Level 3 requires BS with 6–8 years or MS with 4–6 years in ASIC/FPGA design, in an R&D setting.

Proficiency in SystemVerilog and tools (Xilinx Vivado, Intel Quartus, Synopsys Synplify) is required; C coding and UVM are highly preferred. US citizenship is mandatory for this role.

Qualifications

• Requires 4+ years of experience with ASIC & FPGA design tools (Xilinx Vivado, Intel Quartus, Synopsys Synplify).
• Proficient in SystemVerilog.
• Proficiency with HDL simulators, waveform viewers, and coverage tools.
• Familiarity with hardware-in-the-loop (HIL) test setups and JTAG/logic analyzers.

Responsibilities

• ASIC & FPGA development on an R&D program.
• Develop, test, and integrate DSP, high-speed digital design, and SoC on FPGA platforms.

Skills

SystemVerilog

C coding

UVM

HDL simulators

test equipment knowledge

Education

BS in EE/CS or related field

MS in EE/CS or related field

Tools

Xilinx Vivado

Intel Quartus

Synopsys Synplify

Job description

ONSITE FPGA Design Engineers (4 needs) in either Cherry Hill, NJ or Owego, NY areas

Level 3: BS+6-8 YRS or MS+4-6 YRS

DUR: YR+

This is NOT a Verification position

MUST have exp w/ ASIC & FPGA design tools: SystemVerilog, Xilinx Vivado, Intel Quartus, Synopsys Synplify

Preferred exp with C coding or UVM

***MUST have a U.S. Citizenship***

PROJECT SCOPE:

• The selected candidate will be responsible for ASIC & FPGA development on R&D program.
• This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SoC) implemented on FPGA platforms.
• Experience with COTS based control platforms and embedded processors onFPGA platforms.
• This person will help develop more affordable ways to automate and develop scripts to improve FPGA development efforts. Cross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts.
• The selected candidate will also provide support and technical direction to junior engineers. Overall contribution to design, simulation, verification, integration & test of complex, high speed products.

REQUIREMENTS:

• 4+ years of experience with ASIC & FPGA design tools (Xilinx Vivado, Intel Quartus, Synopsys Synplify).
• Proficient in SystemVerilog
• Proficiency with HDL simulators, waveform viewers, and coverage tools.
• Familiarity with hardware-in-the-loop (HIL) test setups and test equipment (JTAG, logic analyzers).
• Experience with version control tools and configuration management.

HIGHLY DESIRED:

• Proficient in C coding and UVM.

Equal Opportunity Employer/Veterans/Disabled