FPGA Design Engineer (ASIC/FPGA, DSP/RF) – C2C

Elevateprimesolutions; Sunnyvale (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Elevateprimesolutions is seeking a highly skilled FPGA Design Engineer to support an advanced R&D program in Sunnyvale, CA. The position focuses on ASIC/FPGA design, DSP/RF systems, and high-speed data processing architectures. Candidates must have active Secret Clearance and 8-15+ years of experience in FPGA/ASIC design.

The ideal candidate will be hands-on, technically strong, and able to contribute to system design and integration. Interested candidates should share their resume at [e-mail].

Qualifications

• 8-15+ years of experience in FPGA/ASIC design.
• Active Secret Clearance is mandatory.
• Strong background in defense/aerospace or high-performance embedded systems.

Responsibilities

• Support advanced R&D program for FPGA and ASIC design.
• Contribute to complex system design, verification, and integration.
• Work onsite in Sunnyvale, CA.

Skills

FPGA Design

ASIC/FPGA development lifecycle

DSP and RF/Radio systems

SpyGlass (linting, CDC, RTL analysis)

High-speed digital design

Job description

Work Authorization: USC/GC Only (Active Secret Clearance Required - Mandatory)

Interview Process: 1-2 Video Interviews

Role Overview

Client seeks a highly skilled FPGA Design Engineer to support an advanced R&D program.

This role is within a cutting‑edge aerospace/defense environment, focusing on ASIC/FPGA design, DSP/RF systems, and high‑speed data processing architectures. The ideal candidate will be hands‑on, technically strong, and capable of contributing to complex system design, verification, and integration.

Mandatory Requirement (Strict – Do Not Submit Without This)

Active Secret Clearance (must be currently active)

Must‑Have Technical Skills

• Strong hands‑on experience in FPGA Design (core requirement)
• Experience with ASIC/FPGA development lifecycle
• Solid experience in DSP and RF/Radio systems
• Experience with SpyGlass (linting, CDC, RTL analysis)
• Strong understanding of high‑speed digital design and networking concepts

Ideal Candidate Profile

• 8-15+ years of experience in FPGA/ASIC design
• Strong background in defense/aerospace or high‑performance embedded systems
• Experience working in R&D or advanced engineering environments
• Deep understanding of DSP/RF concepts and high‑speed systems
• Comfortable working onsite in Sunnyvale, CA or Littleton, CO

Interested candidate please share your resume at [e-mail]