Foundry Technology Engineer

020 Cisco Systems, Inc.; Holmdel Township (NJ); On-site; USD 137,000 - 228,000; Full time

Benefits offered by this job

Healthcare

401(k) Match

Parental Leave

Paid Holidays

Paid Vacation

RSU grants

Job summary

Cisco Systems, Inc. seeks an accomplished engineer to join the Component Quality and Technology team (CQT) to drive silicon photonics and electronic IC development for high-volume manufacturing.

You will interface between Cisco engineering and foundries, translating design intent into manufacturable, reliable solutions. Responsibilities include managing tape-out lifecycles, developing photonic/electronic process flows, and leading joint development with external foundries to achieve robust

Qualifications

• PhD or MS in Electrical Engineering, Optics, Photonics, or related field.
• 4+ years of validated experience in chip development, foundry engagement, and process qualification in high-volume production.
• Experience with external foundries (e.g., TSMC, GlobalFoundries, Tower) on process bring-up is highly desired.
• Knowledge in DFM/DFR/DFT applied to PIC and EIC fabrication, integration, and characterization.

Responsibilities

• Foundry engagement: manage PIC and EIC tape-out lifecycle from PDK engagement to DRC sign-off and process qualification.
• Process engineering: develop, modify, and optimize photonic and electronic process flows across SiPh and CMOS platforms; emphasize DFM and yield.
• Advanced electronic photonic integration: lead wafer-scale EIC-PIC integration using Wafer-to-Wafer and Die-to-Wafer methods.
• Quality & yield optimization: conduct root-cause analysis and DOE to address failure mechanisms and drive process qualification.

Skills

PhD/MS in EE

Chip development

Foundry engagement

Process qualification

DFM/DFR/DFT

Cadence Virtuoso

Synopsys

Klayout

Education

MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Synopsys

KLayout

Job description

About This Role

We are seeking an accomplished Engineer to join Cisco’s Component Quality and Technology team (CQT), driving the development and integration of next-generation Silicon Photonics (SiPh) and Electronic Integrated Circuits (EICs). In this role, you will serve as the technical interface between Cisco engineering and high-volume manufacturing (HVM) foundries, owning end-to-end process integration and qualification. You will translate design intent into manufacturable, reliable, and testable solutions that power the future of global networking.

Key Responsibilities

• Foundry Engagement: Manage the end-to-end PIC and EIC tape-out lifecycle - from PDK engagement through DRC sign-off, process integration, and process qualification. Drive bring-up of electronic-photonic integration technology platforms in partnership with internal design and external foundry teams.
• Process Engineering: Develop, modify, and optimize photonic and electronic process flows across SiPh and CMOS platforms by leveraging CMOS fabrication capabilities. Conceptualize and execute critical process modules with a strong emphasis on design-for-manufacturing (DFM) principles, ensuring robust process windows and high yield from initial integration through HVM ramp.
• Advanced Electronic Photonic Integration: Lead and optimize wafer-scale processes for advanced EIC-PIC integration using Wafer-to-Wafer and Die-to-Wafer methods, focusing on co-design and co-fabrication strategies.
• Quality & Yield Optimization: Execute root-cause analysis and Design of Experiments (DOE) to address failure mechanisms in discrete and integrated components. Apply design-for-reliability (DFR) frameworks to anticipate and eliminate failure modes early in the development cycle, and drive process qualification.

Minimum requirements

• PhD or MS in Electrical Engineering, Optics, Photonics, or a related field.
• 4+ years of validated experience in chip development, foundry engagement, and process qualification, with demonstrated success in high-volume production environments.
• Direct experience working with external foundries (e.g., TSMC, GlobalFoundries, Tower, or comparable SiPh foundries) on process bring-up is highly desired.
• Knowledge in the design-for-manufacturing (DFM), design-for-reliability (DFR), and design-for-test (DFT) principles applied to the fabrication, integration, and characterization of PIC and EIC devices, across the full device lifecycle from early-stage design review through sustained HVM.
• Proficient in IC design tools including Cadence Virtuoso, Synopsys, and Klayout.

Preferred Qualifications

• Hands-on experience with hybrid bonding and thin-wafer processing.
• Familiarity or hands-on experience with near-package optics (NPO) or co-packaged optics (CPO) architectures is a plus.
• Proven ability to work in cross-functional technical teams and lead vendor/foundry relationships.
• Demonstrated ability to contribute to and lead projects within matrixed, geographically distributed technical teams.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Salary and Benefits

The starting salary range posted for this position is $154,900.00 to $225,300.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

New York City Metro Area: $154,900.00 - $259,100.00
Non-Metro New York state & Washington state: $136,500.00 - $228,300.00

• Medical, dental and vision insurance
• A 401(k) plan with a Cisco matching contribution
• Paid parental leave
• Short and long-term disability coverage
• Basic life insurance
• 10 paid holidays per full calendar year
• 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday
• Paid year-end holiday shutdown
• 4 paid days off for personal wellness determined by Cisco
• 16 days of paid vacation time per full calendar year (Non-exempt employees)
• Accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• Up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• Employees may also receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time
• Employees eligible to earn annual bonuses subject to Cisco’s policies (for non-sales roles)
• Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan
• For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation
• For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target
• Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid