Field-Programmable Gate Arrays Engineer

NJF Global Holdings Ltd; Chicago (IL); On-site; USD 140,000 - 170,000; Full time

Benefits offered by this job

Healthcare and dental benefits

Retirement plan

Life and disability insurance

Generous annual leave

Flexible spending and health savings

Meals and refreshments

Professional development opportunities

Collaborative engineering culture

Job summary

NJF Global Holdings Ltd is seeking a Junior FPGA Design & Verification Engineer to join its hardware team building ultra-low-latency trading infrastructure.

You will design, verify, and validate FPGA solutions, focusing on simulation, verification, automation, and testing. Collaborate with software and hardware engineers to deliver reliable FPGA implementations.

Qualifications

• Degree or equivalent in a relevant engineering field.
• Strong foundation in digital design and verification concepts.

Responsibilities

• Assist with development of synthesizable SystemVerilog code for FPGA-based applications.
• Design and maintain verification environments and automated testbenches.
• Run simulations, debug hardware behavior and analyze waveform data.
• Develop Python-based automation tools to streamline testing and validation.
• Support hardware deployment by investigating performance issues and real-time data.
• Produce clear technical documentation for designs, testing, and verification.

Skills

SystemVerilog

Verilog

Python

Synchronous design

Finite state machines

Clock domain crossing

FIFO architectures

Problem solving

Education

Electrical Engineering / Computer Engineering / Computer Science

Tools

ModelSim

Questa

Vivado Simulator

Job description

Our client is a leading proprietary trading and technology firm that develops cutting-edge hardware and software to support high-performance electronic trading across global financial markets. They are continuing to invest heavily in their engineering capabilities and are looking for an ambitious FPGA Design & Verification Engineer to join their growing hardware team.

This is an excellent opportunity to work alongside experienced FPGA engineers, contributing to the development of ultra-low latency trading systems where performance, reliability, and precision are critical.

The Role

As a Junior FPGA Design & Verification Engineer, you will become part of a collaborative engineering team responsible for designing, verifying, and validating FPGA solutions that power high-performance trading infrastructure.

Working closely with senior hardware engineers, you will gain hands-on experience across the FPGA development lifecycle, with a strong focus on simulation, verification, automation, and testing. You'll help ensure hardware designs perform reliably in production while supporting the development of next-generation low-latency systems.

Key responsibilities include:

• Assisting with the development of synthesizable SystemVerilog code for FPGA-based applications
• Designing and maintaining verification environments and automated testbenches
• Running simulations, debugging hardware behaviour, and analysing waveform dataDeveloping Python-based automation tools to streamline testing and validation
• Supporting hardware deployment by investigating performance issues and analysing real-time data
• Producing clear technical documentation for designs, testing, and verification activities
• Collaborating with software and hardware engineers to deliver reliable, high-performance FPGA solutions

About You

We're looking for someone with a genuine passion for digital hardware design and verification who is eager to develop their skills in a fast-paced engineering environment.

You’ll ideally have:

• A degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline
• Around 1-3 years of commercial, internship, or research experience working with FPGA technologies
• A solid understanding of SystemVerilog or Verilog
• Experience using simulation and verification tools such as ModelSim, Questa, or Vivado Simulator
• Strong Python programming skills for automation and testing
• Good knowledge of synchronous digital design concepts, including finite state machines, clock domain crossing, and FIFO architectures
• Strong analytical and problem-solving abilities with excellent attention to detail

The following would be advantageous but is not essential:

• Experience with PCIe, Ethernet, or DDR memory interfaces
• An understanding of FPGA implementation flows and hardware debugging
• An interest in financial markets, electronic trading, or low-latency systems

What's on Offer

• Competitive base salary from $150,000, with a performance-related bonus
• Comprehensive healthcare, dental and vision cover
• Retirement savings plan with employer contributions
• Company-funded life and disability insurance
• Generous annual leave
• Flexible spending and health savings plans
• Complimentary meals and refreshments
• The opportunity to work with leading engineers on cutting-edge FPGA technology in one of the world's most demanding low-latency environments
• A collaborative, flat-structured engineering culture with excellent opportunities for professional development