Fellow - FPGA architecture

Advanced Micro Devices; San Jose (CA); On-site; USD 150,000 - 200,000; Full time

Benefits offered by this job

Competitive benefits

Diversity and inclusion initiatives

Job summary

Advanced Micro Devices is seeking a Fellow Architect to lead the architecture for its adaptive FPGA devices in San Jose, California. The role involves defining next-generation configuration for secure and scalable programmable logic. Ideal candidates should possess extensive expertise in FPGA architecture and experience in ASIC/SoC design.

You will collaborate with silicon and design teams, driving innovation while mentoring architects. The company offers competitive benefits and values diversity and inclusion.

Qualifications

• Expertise in FPGA architecture with configuration and Partial Reconfiguration.
• Understanding of bitstream, protocols, boot flows, security, and debug.
• Experience in ASIC/SoC design for effective integration.

Responsibilities

• Own FPGA configuration architecture and drive next-generation updates.
• Define Partial Reconfiguration architecture for secure dynamic updates.
• Architect readback and observability infrastructure for validation.

Skills

FPGA configuration architecture

Partial Reconfiguration

Security protocols

ASIC/SoC design

Debug and observability infrastructure

Education

BS, MS, or PhD in Electrical/Computer Engineering

Tools

FPGA toolchains (synthesis, P&R)

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE

We are seeking a Fellow Architect to define and drive next‑generation architecture for AMD’s adaptive FPGA devices. This role will own the architecture for FPGA configuration, readback, and Partial Reconfiguration (PR), enabling scalable, secure, and flexible deployment of programmable logic in heterogeneous SoC and chiplet environments.

As a senior technical leader, you will shape the long‑term vision for bitstream architecture, configuration flows, runtime reconfiguration, debug observability, and system integration, translating customer requirements across Emulation & Prototyping, AI, Data Center, Embedded, and Automotive into differentiated FPGA capabilities. You will collaborate across silicon, RTL, tools, software, and customer teams.

THE PERSON

You are a recognized expert in FPGA architecture with deep expertise of Configuration and Partial Reconfiguration. You have strong understanding of configuration architecture including bitstream, protocols, boot flows, security, readback and debug. You have deep appreciation of trade‑offs across reliability, performance, power, and robustness. You are a proven advocate and practitioner of Partial Reconfiguration at system scale. You have experience in ASIC/SoC design, enabling effective integration with hardened subsystems and modern interconnects.

You bring clarity to complex problems and influence technical direction across organizations.

KEY RESPONSIBILITIES

• Own FPGA configuration architecture, including bitstream, boot flows, interfaces, compression, security, and reliability
• Define next‑generation Partial Reconfiguration architecture for low‑latency, secure dynamic updates
• Drive innovation in runtime reconfiguration for high‑availability and adaptive systems
• Architect readback, debug, and observability infrastructure for validation and in‑field diagnostics
• Define configuration security, including secure boot, key management, and update flows
• Drive system trade‑offs across configuration bandwidth, latency, and power, including memory and interconnect interactions
• Develop clear architecture specifications for configuration, PR, and debug subsystems
• Align with software/tools teams for end‑to‑end configuration and PR flows
• Collaborate with silicon and design teams for scalable high‑quality implementation
• Influence product roadmap and customer engagement for PR‑driven solutions
• Mentor architects and elevate FPGA architecture standards across the organization

PREFERRED EXPERIENCE

• Strong Expertise in FPGA configuration, Partial Reconfiguration, and bitstream architecture
• Experience with readback/debug infrastructure and field diagnostics
• Background in ASIC/SoC design flows
• Familiarity with FPGA toolchains (synthesis, P&R, PR flows)
• Ability to define architecture across silicon, tools, and software layers

ACADEMIC CREDENTIALS

• BS, MS, or PhD in Electrical/Computer Engineering or related field
• Recognized technical leader in FPGA systems or architecture with significant architectural contributions, patents, publications, or industry impact

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s ‘Responsible AI Policy’ is available here.

This posting is for an existing vacancy.