ESD CAD Engineer

Intel Corporation; Santa Clara (CA); On-site; USD 100,000 - 150,000; Full time

Job summary

Intel's Design Enablement organization seeks an ESD CAD Engineer to develop PERC ESD rule decks and collaborate with design teams. Ideal candidates will have MS/PhD degrees and experience with ESD/Latch-up models, ensuring the integration of cutting-edge technologies. Join Intel and help bring smart devices to market faster.

Benefits

Competitive pay

Stock options

Bonuses

Health benefits

Retirement programs

Vacation benefits

Qualifications

• MS or PhD in Electrical/Computer Engineering with relevant experience.
• 3+ years in ESD/Latch-up Pre-Si models.
• Experience with industry-standard ESD tools.

Responsibilities

• Develop PERC ESD rule decks for latest Intel technologies.
• Collaborate with design teams to meet ESD protection requirements.
• Work with PDK team to develop and maintain PDKs.

Skills

Calibre

ICV

Pegasus PERC

Debugging

Scripting languages

Education

MS degree in Electrical Engineering

PhD degree in Electrical Engineering

Job description

Intel is the world’s largest chip manufacturer, and it strives to make every facet of semiconductor manufacturing state-of-the-art, from semiconductor process development and manufacturing to yield improvement, packaging, final test and optimization, and world-class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Job Description

Intel’s Design Enablement (DE) organization is looking for an ESD CAD Engineer to join the PERC ESD development team. The successful candidate will be responsible for developing PERC ESD rule decks for the latest Intel technologies. This work will directly enable design teams to get to market faster with leadership products on cutting-edge technologies.

Responsibilities

• Develop PERC ESD rule decks for latest Intel technologies
• Collaborate with design teams to ensure that ESD protection requirements are met
• Work with the PDK team to develop and maintain PDKs for Intel’s most advanced process technologies
• Drive PDKs towards industry standard methods and ease of use for end customers
• Stay up-to-date on the latest ESD protection technologies and methodologies

Qualifications

Minimum Qualifications:

• MS degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience
• PhD degree in Electrical Engineering, Computer Engineering, or related field with 1+ years of experience
• 3+ years of experience with Calibre, ICV, or Pegasus PERC tools
• Experience with ESD/Latch-up Pre-Si models

Preferred Qualifications:

• 3+ years of experience with HBM and CDM
• I/O design and methodologies
• Debugging skills
• Experience in writing physical verification runsets
• Experience in extraction and physical design domain
• Experience in scripting languages for QA automation
• Experience in driving cross-functional and industry-wide initiatives and taskforces
• Knowledge of semiconductor device physics, process technology, and design rules

Intel offers a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.

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