Emulation Engineer - Hardware Prototyping (HAPS)

Etched; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across inference workloads.

Join a team of engineers tackling RTL bring-up, PCIe, memory models, and cross-functional collaboration with software, firmware, DV, and tooling partners to scale our platform beyond current limits.

Qualifications

• Experience bringing up FPGA/ASIC subsystems in hardware platforms.
• Ability to collaborate with firmware, software and DV teams.

Responsibilities

• Own HAPS bring-up. Get RTL running on prototype with partitioning, timing closure, clocking, memory mapping and full-chip assembly.
• Expand platform coverage by standing up new subsystem configurations.
• Support users by triaging failures and determining root cause across RTL/firmware/platform.
• Debug hard problems using waveform capture and protocol analyzers.
• Bring up interfaces (PCIe, Ethernet, HBM, memory models, JTAG, I2C, UART, QSPI).
• Build automated build/regression/image delivery flows.

Skills

RTL debugging

FPGA

Firmware troubleshooting

PCIe

JTAG

C/C++

Tools

Vivado

ModelSim

Waveform analysis

Protocol analyzers

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

What you'll do

• Own HAPS bring-up. Take RTL from the design teams and get it running on the prototype - partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly.

• Expand platform coverage. Stand up new subsystem configurations so more of the chip is available to software earlier. Each new partition you enable unblocks a team.

• Support your users. Firmware, driver, and software engineers are your customers. You'll help them get running, triage their failures, and figure out whether the bug is theirs, the RTL's, or the platform's.

• Debug hard problems. Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling you have to build yourself.

• Bring up interfaces. PCIe, Ethernet, HBM and memory models, JTAG, I2C, UART, QSPI - both the models and the physical bridges.

• Build the flows. Automate builds, regressions, and image delivery so the platform scales past the number of people who understand it.

• Work across the org. Design, DV, Silicon Validation, Performance, Firmware, and Software - plus direct partnership with Synopsys on tool issues and platform capability.

Representative projects

• Bring up a new subsystem partition on HAPS and get firmware booting on it end to end.

• Build a self-service flow that lets software users load and run their own images without prototyping support in the loop.

• Instrument deep trace capture across partition boundaries and build the tooling that surfaces it usefully.

• Create configurable chip-to-chip and off-chip interface models using prototyping-efficient primitives.

• Close timing on a partition that doesn't want to close, and document how you