EDA Design Flow Development Engineer

Intel; Hillsboro (OR); Hybrid; USD 141,910 - 269,100; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement benefits

Vacation time

Job summary

Intel is hiring an experienced EDA Tools Hardware Engineer to develop and maintain transistor-level reliability verification methodologies, focusing on power integrity for advanced semiconductor technologies. The role requires collaboration across multiple teams to innovate scalable EM and IR analysis.

The ideal candidate will have a strong background in electrical engineering with a bachelor's degree and significant experience in electromigration reliability concepts. This position is supported by a competitive compensation package and a hybrid work model.

Qualifications

• 6+ years of experience in relevant fields.
• Experience with CAD methodology and automation infrastructure.
• Knowledge of power integrity analysis flows.

Responsibilities

• Develop and maintain transistor‑level EM and IR drop analysis flows.
• Work closely with circuit design, package, and signoff teams.
• Enable accurate EM/IR analysis methodologies for advanced-node designs.

Skills

EM/IR reliability concepts (Electromigration and Power Drop)

Experience with Redhawk/Totem tools

Scripting and automation skills in Linux environments

Education

Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field

Master’s degree (4+ years of experience)

PhD (2+ years of experience)

Job description

Role and Impact

Join Intel in shaping the future of technology. As an EDA Tools Hardware Engineer, you will play a pivotal role in enabling groundbreaking innovations that power Intel’s leadership in semiconductor design and manufacturing. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor‑level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed‑signal interfaces, and high‑performance custom macros across advanced semiconductor technologies.

This role focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor‑level reliability verification. The engineer will work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced‑node designs.

Qualifications

Minimum Qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field, and 6+ years of experience; 4+ years of experience with a Master’s degree; or 2+ years of experience with a PhD.
• EM/IR reliability concepts (Electromigration and Power Drop).
• Experience with Redhawk/Totem tools.

Preferred Qualifications

• CMOS circuit operation.
• Power delivery networks.
• SPICE simulation.
• Parasitic extraction fundamentals.
• Advanced‑node design challenges.
• Transistor‑level power integrity analysis flows.
• Scripting and automation skills in Linux environments.

Job Information

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.